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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/sound/mediatek,mt8189-afe-pcm.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: MediaTek Audio Front End PCM controller for MT8189 |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Darren Ye <darren.ye@mediatek.com> |
| 11 | + - Cyril Chao <cyril.chao@mediatek.com> |
| 12 | + |
| 13 | +properties: |
| 14 | + compatible: |
| 15 | + const: mediatek,mt8189-afe-pcm |
| 16 | + |
| 17 | + reg: |
| 18 | + maxItems: 1 |
| 19 | + |
| 20 | + interrupts: |
| 21 | + maxItems: 1 |
| 22 | + |
| 23 | + memory-region: |
| 24 | + maxItems: 1 |
| 25 | + |
| 26 | + mediatek,apmixedsys: |
| 27 | + $ref: /schemas/types.yaml#/definitions/phandle |
| 28 | + description: To set up the apll12 tuner |
| 29 | + |
| 30 | + power-domains: |
| 31 | + maxItems: 1 |
| 32 | + |
| 33 | + clocks: |
| 34 | + items: |
| 35 | + - description: mux for audio intbus |
| 36 | + - description: mux for audio engen1 |
| 37 | + - description: mux for audio engen2 |
| 38 | + - description: mux for audio h |
| 39 | + - description: audio apll1 clock |
| 40 | + - description: audio apll2 clock |
| 41 | + - description: audio apll1 divide4 |
| 42 | + - description: audio apll2 divide4 |
| 43 | + - description: audio apll12 divide for i2sin0 |
| 44 | + - description: audio apll12 divide for i2sin1 |
| 45 | + - description: audio apll12 divide for i2sout0 |
| 46 | + - description: audio apll12 divide for i2sout1 |
| 47 | + - description: audio apll12 divide for fmi2s |
| 48 | + - description: audio apll12 divide for tdmout mck |
| 49 | + - description: audio apll12 divide for tdmout bck |
| 50 | + - description: mux for audio apll1 |
| 51 | + - description: mux for audio apll2 |
| 52 | + - description: mux for i2sin0 mck |
| 53 | + - description: mux for i2sin1 mck |
| 54 | + - description: mux for i2sout0 mck |
| 55 | + - description: mux for i2sout1 mck |
| 56 | + - description: mux for fmi2s mck |
| 57 | + - description: mux for tdmout mck |
| 58 | + - description: 26m clock |
| 59 | + - description: audio slv clock |
| 60 | + - description: audio mst clock |
| 61 | + - description: audio intbus clock |
| 62 | + |
| 63 | + clock-names: |
| 64 | + items: |
| 65 | + - const: top_aud_intbus |
| 66 | + - const: top_aud_eng1 |
| 67 | + - const: top_aud_eng2 |
| 68 | + - const: top_aud_h |
| 69 | + - const: apll1 |
| 70 | + - const: apll2 |
| 71 | + - const: apll1_d4 |
| 72 | + - const: apll2_d4 |
| 73 | + - const: apll12_div_i2sin0 |
| 74 | + - const: apll12_div_i2sin1 |
| 75 | + - const: apll12_div_i2sout0 |
| 76 | + - const: apll12_div_i2sout1 |
| 77 | + - const: apll12_div_fmi2s |
| 78 | + - const: apll12_div_tdmout_m |
| 79 | + - const: apll12_div_tdmout_b |
| 80 | + - const: top_apll1 |
| 81 | + - const: top_apll2 |
| 82 | + - const: top_i2sin0 |
| 83 | + - const: top_i2sin1 |
| 84 | + - const: top_i2sout0 |
| 85 | + - const: top_i2sout1 |
| 86 | + - const: top_fmi2s |
| 87 | + - const: top_dptx |
| 88 | + - const: clk26m |
| 89 | + - const: aud_slv_ck_peri |
| 90 | + - const: aud_mst_ck_peri |
| 91 | + - const: aud_intbus_ck_peri |
| 92 | + |
| 93 | +required: |
| 94 | + - compatible |
| 95 | + - reg |
| 96 | + - interrupts |
| 97 | + - memory-region |
| 98 | + - power-domains |
| 99 | + - clocks |
| 100 | + - clock-names |
| 101 | + |
| 102 | +additionalProperties: false |
| 103 | + |
| 104 | +examples: |
| 105 | + - | |
| 106 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 107 | + #include <dt-bindings/interrupt-controller/irq.h> |
| 108 | +
|
| 109 | + soc { |
| 110 | + #address-cells = <2>; |
| 111 | + #size-cells = <2>; |
| 112 | +
|
| 113 | + afe@11050000 { |
| 114 | + compatible = "mediatek,mt8189-afe-pcm"; |
| 115 | + reg = <0 0x11050000 0 0x10000>; |
| 116 | + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; |
| 117 | + memory-region = <&afe_dma_mem_reserved>; |
| 118 | + pinctrl-names = "default"; |
| 119 | + pinctrl-0 = <&aud_pins_default>; |
| 120 | + power-domains = <&scpsys 1>; //MT8189_POWER_DOMAIN_AUDIO |
| 121 | + clocks = <&topckgen_clk 23>, //CLK_TOP_AUD_INTBUS_SEL |
| 122 | + <&topckgen_clk 39>, //CLK_TOP_AUD_ENGEN1_SEL |
| 123 | + <&topckgen_clk 40>, //CLK_TOP_AUD_ENGEN2_SEL |
| 124 | + <&topckgen_clk 49>, //CLK_TOP_AUDIO_H_SEL |
| 125 | + <&topckgen_clk 146>, //CLK_TOP_APLL1 |
| 126 | + <&topckgen_clk 151>, //CLK_TOP_APLL2 |
| 127 | + <&topckgen_clk 148>, //CLK_TOP_APLL1_D4 |
| 128 | + <&topckgen_clk 153>, //CLK_TOP_APLL2_D4 |
| 129 | + <&topckgen_clk 93>, //CLK_TOP_APLL12_CK_DIV_I2SIN0 |
| 130 | + <&topckgen_clk 94>, //CLK_TOP_APLL12_CK_DIV_I2SIN1 |
| 131 | + <&topckgen_clk 95>, //CLK_TOP_APLL12_CK_DIV_I2SOUT0 |
| 132 | + <&topckgen_clk 96>, //CLK_TOP_APLL12_CK_DIV_I2SOUT1 |
| 133 | + <&topckgen_clk 97>, //CLK_TOP_APLL12_CK_DIV_FMI2S |
| 134 | + <&topckgen_clk 98>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M |
| 135 | + <&topckgen_clk 99>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_B |
| 136 | + <&topckgen_clk 44>, //CLK_TOP_AUD_1_SEL |
| 137 | + <&topckgen_clk 45>, //CLK_TOP_AUD_2_SEL |
| 138 | + <&topckgen_clk 78>, //CLK_TOP_APLL_I2SIN0_MCK_SEL |
| 139 | + <&topckgen_clk 79>, //CLK_TOP_APLL_I2SIN1_MCK_SEL |
| 140 | + <&topckgen_clk 84>, //CLK_TOP_APLL_I2SOUT0_MCK_SEL |
| 141 | + <&topckgen_clk 85>, //CLK_TOP_APLL_I2SOUT1_MCK_SEL |
| 142 | + <&topckgen_clk 90>, //CLK_TOP_APLL_FMI2S_MCK_SEL |
| 143 | + <&topckgen_clk 91>, //CLK_TOP_APLL_TDMOUT_MCK_SEL |
| 144 | + <&topckgen_clk 191>, //CLK_TOP_TCK_26M_MX9 |
| 145 | + <&pericfg_ao_clk 77>, //CLK_PERAO_AUDIO0 |
| 146 | + <&pericfg_ao_clk 78>, //CLK_PERAO_AUDIO1 |
| 147 | + <&pericfg_ao_clk 79>; //CLK_PERAO_AUDIO2 |
| 148 | + clock-names = "top_aud_intbus", |
| 149 | + "top_aud_eng1", |
| 150 | + "top_aud_eng2", |
| 151 | + "top_aud_h", |
| 152 | + "apll1", |
| 153 | + "apll2", |
| 154 | + "apll1_d4", |
| 155 | + "apll2_d4", |
| 156 | + "apll12_div_i2sin0", |
| 157 | + "apll12_div_i2sin1", |
| 158 | + "apll12_div_i2sout0", |
| 159 | + "apll12_div_i2sout1", |
| 160 | + "apll12_div_fmi2s", |
| 161 | + "apll12_div_tdmout_m", |
| 162 | + "apll12_div_tdmout_b", |
| 163 | + "top_apll1", |
| 164 | + "top_apll2", |
| 165 | + "top_i2sin0", |
| 166 | + "top_i2sin1", |
| 167 | + "top_i2sout0", |
| 168 | + "top_i2sout1", |
| 169 | + "top_fmi2s", |
| 170 | + "top_dptx", |
| 171 | + "clk26m", |
| 172 | + "aud_slv_ck_peri", |
| 173 | + "aud_mst_ck_peri", |
| 174 | + "aud_intbus_ck_peri"; |
| 175 | + }; |
| 176 | + }; |
| 177 | +
|
| 178 | +... |
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