@@ -1018,8 +1018,9 @@ static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx)
10181018 return 0;
10191019}
10201020
1021- static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx)
1021+ static inline enum imx_i2c_state i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx)
10221022{
1023+ enum imx_i2c_state next_state = IMX_I2C_STATE_READ_CONTINUE;
10231024 unsigned int temp;
10241025
10251026 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) {
@@ -1033,25 +1034,28 @@ static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx)
10331034 i2c_imx->stopped = 1;
10341035 temp &= ~(I2CR_MSTA | I2CR_MTX);
10351036 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1036- } else {
1037- /*
1038- * For i2c master receiver repeat restart operation like:
1039- * read -> repeat MSTA -> read/write
1040- * The controller must set MTX before read the last byte in
1041- * the first read operation, otherwise the first read cost
1042- * one extra clock cycle.
1043- */
1044- temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1045- temp |= I2CR_MTX;
1046- imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1037+
1038+ return IMX_I2C_STATE_DONE;
10471039 }
1040+ /*
1041+ * For i2c master receiver repeat restart operation like:
1042+ * read -> repeat MSTA -> read/write
1043+ * The controller must set MTX before read the last byte in
1044+ * the first read operation, otherwise the first read cost
1045+ * one extra clock cycle.
1046+ */
1047+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1048+ temp |= I2CR_MTX;
1049+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1050+ next_state = IMX_I2C_STATE_DONE;
10481051 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) {
10491052 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
10501053 temp |= I2CR_TXAK;
10511054 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
10521055 }
10531056
10541057 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1058+ return next_state;
10551059}
10561060
10571061static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx)
@@ -1088,11 +1092,9 @@ static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned i
10881092 break;
10891093
10901094 case IMX_I2C_STATE_READ_CONTINUE:
1091- i2c_imx_isr_read_continue(i2c_imx);
1092- if (i2c_imx->msg_buf_idx == i2c_imx->msg->len) {
1093- i2c_imx->state = IMX_I2C_STATE_DONE;
1095+ i2c_imx->state = i2c_imx_isr_read_continue(i2c_imx);
1096+ if (i2c_imx->state == IMX_I2C_STATE_DONE)
10941097 wake_up(&i2c_imx->queue);
1095- }
10961098 break;
10971099
10981100 case IMX_I2C_STATE_READ_BLOCK_DATA:
@@ -1490,6 +1492,7 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
14901492 bool is_lastmsg)
14911493{
14921494 int block_data = msgs->flags & I2C_M_RECV_LEN;
1495+ int ret = 0;
14931496
14941497 dev_dbg(&i2c_imx->adapter.dev,
14951498 "<%s> write slave address: addr=0x%x\n",
@@ -1522,10 +1525,20 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
15221525 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__);
15231526 return -ETIMEDOUT;
15241527 }
1525- if (!i2c_imx->stopped)
1526- return i2c_imx_bus_busy(i2c_imx, 0, false);
1528+ if (i2c_imx->is_lastmsg) {
1529+ if (!i2c_imx->stopped)
1530+ ret = i2c_imx_bus_busy(i2c_imx, 0, false);
1531+ /*
1532+ * Only read the last byte of the last message after the bus is
1533+ * not busy. Else the controller generates another clock which
1534+ * might confuse devices.
1535+ */
1536+ if (!ret)
1537+ i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx,
1538+ IMX_I2C_I2DR);
1539+ }
15271540
1528- return 0 ;
1541+ return ret ;
15291542}
15301543
15311544static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
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