@@ -1722,42 +1722,43 @@ static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
17221722 case RX_MACRO_AIF2_PB :
17231723 case RX_MACRO_AIF3_PB :
17241724 case RX_MACRO_AIF4_PB :
1725- for (j = 0 ; j < INTERP_MAX ; j ++ ) {
1726- reg = CDC_RX_RXn_RX_PATH_CTL (j );
1727- mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL (j );
1728- dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL (j );
1729-
1730- if (mute ) {
1731- snd_soc_component_update_bits (component , reg ,
1732- CDC_RX_PATH_PGA_MUTE_MASK ,
1733- CDC_RX_PATH_PGA_MUTE_ENABLE );
1734- snd_soc_component_update_bits (component , mix_reg ,
1735- CDC_RX_PATH_PGA_MUTE_MASK ,
1736- CDC_RX_PATH_PGA_MUTE_ENABLE );
1737- } else {
1738- snd_soc_component_update_bits (component , reg ,
1739- CDC_RX_PATH_PGA_MUTE_MASK , 0x0 );
1740- snd_soc_component_update_bits (component , mix_reg ,
1741- CDC_RX_PATH_PGA_MUTE_MASK , 0x0 );
1742- }
1743-
1744- if (j == INTERP_AUX )
1745- dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL ;
1725+ for (j = 0 ; j < INTERP_MAX ; j ++ ) {
1726+ reg = CDC_RX_RXn_RX_PATH_CTL (j );
1727+ mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL (j );
1728+ dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL (j );
1729+
1730+ if (mute ) {
1731+ snd_soc_component_update_bits (component , reg ,
1732+ CDC_RX_PATH_PGA_MUTE_MASK ,
1733+ CDC_RX_PATH_PGA_MUTE_ENABLE );
1734+ snd_soc_component_update_bits (component , mix_reg ,
1735+ CDC_RX_PATH_PGA_MUTE_MASK ,
1736+ CDC_RX_PATH_PGA_MUTE_ENABLE );
1737+ } else {
1738+ snd_soc_component_update_bits (component , reg ,
1739+ CDC_RX_PATH_PGA_MUTE_MASK , 0x0 );
1740+ snd_soc_component_update_bits (component , mix_reg ,
1741+ CDC_RX_PATH_PGA_MUTE_MASK , 0x0 );
1742+ }
17461743
1747- int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8 ;
1748- int_mux_cfg1 = int_mux_cfg0 + 4 ;
1749- int_mux_cfg0_val = snd_soc_component_read (component , int_mux_cfg0 );
1750- int_mux_cfg1_val = snd_soc_component_read (component , int_mux_cfg1 );
1744+ if (j == INTERP_AUX )
1745+ dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL ;
17511746
1752- if (snd_soc_component_read (component , dsm_reg ) & 0x01 ) {
1753- if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0 ))
1754- snd_soc_component_update_bits (component , reg , 0x20 , 0x20 );
1755- if (int_mux_cfg1_val & 0x0F ) {
1756- snd_soc_component_update_bits (component , reg , 0x20 , 0x20 );
1757- snd_soc_component_update_bits (component , mix_reg , 0x20 , 0x20 );
1747+ int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8 ;
1748+ int_mux_cfg1 = int_mux_cfg0 + 4 ;
1749+ int_mux_cfg0_val = snd_soc_component_read (component , int_mux_cfg0 );
1750+ int_mux_cfg1_val = snd_soc_component_read (component , int_mux_cfg1 );
1751+
1752+ if (snd_soc_component_read (component , dsm_reg ) & 0x01 ) {
1753+ if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0 ))
1754+ snd_soc_component_update_bits (component , reg , 0x20 , 0x20 );
1755+ if (int_mux_cfg1_val & 0x0F ) {
1756+ snd_soc_component_update_bits (component , reg , 0x20 , 0x20 );
1757+ snd_soc_component_update_bits (component , mix_reg , 0x20 ,
1758+ 0x20 );
1759+ }
17581760 }
17591761 }
1760- }
17611762 break ;
17621763 default :
17631764 break ;
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