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Add support of MediaTek mt8186 to SOF
Merge series from Tinghan Shen <tinghan.shen@mediatek.com>: Add support of MediaTek mt8186 SoC DSP to SOF.
2 parents e5737cc + 0e0b83c commit 85780eb

9 files changed

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‎sound/soc/sof/mediatek/Kconfig‎

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@@ -21,6 +21,15 @@ config SND_SOC_SOF_MTK_COMMON
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This option is not user-selectable but automagically handled by
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'select' statements at a higher level
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config SND_SOC_SOF_MT8186
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tristate "SOF support for MT8186 audio DSP"
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select SND_SOC_SOF_MTK_COMMON
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help
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This adds support for Sound Open Firmware for Mediatek platforms
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using the mt8186 processors.
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Say Y if you have such a device.
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If unsure select "N".
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config SND_SOC_SOF_MT8195
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tristate "SOF support for MT8195 audio DSP"
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select SND_SOC_SOF_MTK_COMMON

‎sound/soc/sof/mediatek/Makefile‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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obj-$(CONFIG_SND_SOC_SOF_MT8195) += mt8195/
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obj-$(CONFIG_SND_SOC_SOF_MT8186) += mt8186/

‎sound/soc/sof/mediatek/adsp_helper.h‎

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@@ -29,6 +29,14 @@ struct mtk_adsp_chip_info {
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void __iomem *shared_dram; /* part of va_dram */
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phys_addr_t adsp_bootup_addr;
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int dram_offset; /*dram offset between system and dsp view*/
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phys_addr_t pa_secreg;
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u32 secregsize;
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void __iomem *va_secreg;
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phys_addr_t pa_busreg;
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u32 busregsize;
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void __iomem *va_busreg;
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};
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struct adsp_priv {

‎sound/soc/sof/mediatek/mt8186/Makefile‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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snd-sof-mt8186-objs := mt8186.o mt8186-clk.o mt8186-loader.o
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obj-$(CONFIG_SND_SOC_SOF_MT8186) += snd-sof-mt8186.o
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‎sound/soc/sof/mediatek/mt8186/mt8186-clk.c‎

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2022 Mediatek Corporation. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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//
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// Hardware interface for mt8186 DSP clock
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include "../../sof-audio.h"
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#include "../../ops.h"
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#include "../adsp_helper.h"
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#include "mt8186.h"
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#include "mt8186-clk.h"
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static const char *adsp_clks[ADSP_CLK_MAX] = {
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[CLK_TOP_AUDIODSP] = "audiodsp_sel",
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[CLK_TOP_ADSP_BUS] = "adsp_bus_sel",
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};
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int mt8186_adsp_init_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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struct device *dev = sdev->dev;
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int i;
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priv->clk = devm_kcalloc(dev, ADSP_CLK_MAX, sizeof(*priv->clk), GFP_KERNEL);
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if (!priv->clk)
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return -ENOMEM;
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for (i = 0; i < ADSP_CLK_MAX; i++) {
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priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
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if (IS_ERR(priv->clk[i]))
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return PTR_ERR(priv->clk[i]);
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}
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return 0;
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}
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static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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struct device *dev = sdev->dev;
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int ret;
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ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(audiodsp) fail %d\n",
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__func__, ret);
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return ret;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BUS]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(adsp_bus) fail %d\n",
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__func__, ret);
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clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
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return ret;
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}
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return 0;
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}
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static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
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clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
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}
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int adsp_clock_on(struct snd_sof_dev *sdev)
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{
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struct device *dev = sdev->dev;
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int ret;
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ret = adsp_enable_all_clock(sdev);
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if (ret) {
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dev_err(dev, "failed to adsp_enable_clock: %d\n", ret);
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return ret;
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}
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN,
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UART_EN | DMA_EN | TIMER_EN | COREDBG_EN | CORE_CLK_EN);
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL,
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UART_BCLK_CG | UART_RSTN);
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return 0;
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}
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void adsp_clock_off(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN, 0);
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL, 0);
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adsp_disable_all_clock(sdev);
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}
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‎sound/soc/sof/mediatek/mt8186/mt8186-clk.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* Copyright (c) 2022 MediaTek Corporation. All rights reserved.
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*
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* Header file for the mt8186 DSP clock definition
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*/
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#ifndef __MT8186_CLK_H
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#define __MT8186_CLK_H
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struct snd_sof_dev;
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/* DSP clock */
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enum adsp_clk_id {
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CLK_TOP_AUDIODSP,
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CLK_TOP_ADSP_BUS,
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ADSP_CLK_MAX
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};
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int mt8186_adsp_init_clock(struct snd_sof_dev *sdev);
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int adsp_clock_on(struct snd_sof_dev *sdev);
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void adsp_clock_off(struct snd_sof_dev *sdev);
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#endif

‎sound/soc/sof/mediatek/mt8186/mt8186-loader.c‎

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright (c) 2022 Mediatek Corporation. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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//
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// Hardware interface for mt8186 DSP code loader
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#include <sound/sof.h>
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#include "mt8186.h"
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#include "../../ops.h"
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void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
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{
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/* set RUNSTALL to stop core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* set core boot address */
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);
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/* assert core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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SW_RSTN_C0 | SW_DBG_RSTN_C0);
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/* hardware requirement */
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udelay(1);
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/* release core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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0);
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/* clear RUNSTALL (bit31) to start core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, 0);
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}
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void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
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{
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/* set RUNSTALL to stop core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* assert core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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SW_RSTN_C0 | SW_DBG_RSTN_C0);
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}
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