Skip to content

Commit 9cd8273

Browse files
Stefan Bindingtiwai
Stefan Binding
authored and
tiwai
committed
ALSA: hda/cs8409: Use general cs42l42 include in cs8409 hda driver
This is to improve maintainability of the driver. Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220504161236.2490532-3-sbinding@opensource.cirrus.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
1 parent 7b43e6d commit 9cd8273

3 files changed

Lines changed: 229 additions & 231 deletions

File tree

‎sound/pci/hda/patch_cs8409-tables.c‎

Lines changed: 162 additions & 162 deletions
Original file line numberDiff line numberDiff line change
@@ -78,65 +78,65 @@ const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
7878

7979
/* Vendor specific HW configuration for CS42L42 */
8080
static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
81-
{ 0x1010, 0xB0 },
82-
{ 0x1D01, 0x00 },
81+
{ CS42L42_I2C_TIMEOUT, 0xB0 },
82+
{ CS42L42_ADC_CTL, 0x00 },
8383
{ 0x1D02, 0x06 },
84-
{ 0x1D03, 0x9F },
85-
{ 0x1107, 0x01 },
86-
{ 0x1009, 0x02 },
87-
{ 0x1007, 0x03 },
88-
{ 0x1201, 0x00 },
89-
{ 0x1208, 0x13 },
90-
{ 0x1205, 0xFF },
91-
{ 0x1206, 0x00 },
92-
{ 0x1207, 0x20 },
93-
{ 0x1202, 0x0D },
94-
{ 0x2A02, 0x02 },
95-
{ 0x2A03, 0x00 },
96-
{ 0x2A04, 0x00 },
97-
{ 0x2A05, 0x02 },
98-
{ 0x2A06, 0x00 },
99-
{ 0x2A07, 0x20 },
100-
{ 0x2A08, 0x02 },
101-
{ 0x2A09, 0x00 },
102-
{ 0x2A0A, 0x80 },
103-
{ 0x2A0B, 0x02 },
104-
{ 0x2A0C, 0x00 },
105-
{ 0x2A0D, 0xA0 },
106-
{ 0x2A01, 0x0C },
107-
{ 0x2902, 0x01 },
108-
{ 0x2903, 0x02 },
109-
{ 0x2904, 0x00 },
110-
{ 0x2905, 0x00 },
111-
{ 0x2901, 0x01 },
112-
{ 0x1101, 0x0A },
113-
{ 0x1102, 0x84 },
114-
{ 0x2301, 0x3F },
115-
{ 0x2303, 0x3F },
116-
{ 0x2302, 0x3f },
117-
{ 0x2001, 0x03 },
118-
{ 0x1B75, 0xB6 },
119-
{ 0x1B73, 0xC2 },
120-
{ 0x1129, 0x01 },
121-
{ 0x1121, 0xF3 },
122-
{ 0x1103, 0x20 },
123-
{ 0x1105, 0x00 },
124-
{ 0x1112, 0x00 },
125-
{ 0x1113, 0x80 },
126-
{ 0x1C03, 0xC0 },
127-
{ 0x1101, 0x02 },
128-
{ 0x1316, 0xff },
129-
{ 0x1317, 0xff },
130-
{ 0x1318, 0xff },
131-
{ 0x1319, 0xff },
132-
{ 0x131a, 0xff },
133-
{ 0x131b, 0xff },
134-
{ 0x131c, 0xff },
135-
{ 0x131e, 0xff },
136-
{ 0x131f, 0xff },
137-
{ 0x1320, 0xff },
138-
{ 0x1b79, 0xff },
139-
{ 0x1b7a, 0xff },
84+
{ CS42L42_ADC_VOLUME, 0x9F },
85+
{ CS42L42_OSC_SWITCH, 0x01 },
86+
{ CS42L42_MCLK_CTL, 0x02 },
87+
{ CS42L42_SRC_CTL, 0x03 },
88+
{ CS42L42_MCLK_SRC_SEL, 0x00 },
89+
{ CS42L42_ASP_FRM_CFG, 0x13 },
90+
{ CS42L42_FSYNC_P_LOWER, 0xFF },
91+
{ CS42L42_FSYNC_P_UPPER, 0x00 },
92+
{ CS42L42_ASP_CLK_CFG, 0x20 },
93+
{ CS42L42_SPDIF_CLK_CFG, 0x0D },
94+
{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
95+
{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
96+
{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
97+
{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
98+
{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
99+
{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
100+
{ CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x02 },
101+
{ CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
102+
{ CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x80 },
103+
{ CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x02 },
104+
{ CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
105+
{ CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0xA0 },
106+
{ CS42L42_ASP_RX_DAI0_EN, 0x0C },
107+
{ CS42L42_ASP_TX_CH_EN, 0x01 },
108+
{ CS42L42_ASP_TX_CH_AP_RES, 0x02 },
109+
{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
110+
{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
111+
{ CS42L42_ASP_TX_SZ_EN, 0x01 },
112+
{ CS42L42_PWR_CTL1, 0x0A },
113+
{ CS42L42_PWR_CTL2, 0x84 },
114+
{ CS42L42_MIXER_CHA_VOL, 0x3F },
115+
{ CS42L42_MIXER_CHB_VOL, 0x3F },
116+
{ CS42L42_MIXER_ADC_VOL, 0x3f },
117+
{ CS42L42_HP_CTL, 0x03 },
118+
{ CS42L42_MIC_DET_CTL1, 0xB6 },
119+
{ CS42L42_TIPSENSE_CTL, 0xC2 },
120+
{ CS42L42_HS_CLAMP_DISABLE, 0x01 },
121+
{ CS42L42_HS_SWITCH_CTL, 0xF3 },
122+
{ CS42L42_PWR_CTL3, 0x20 },
123+
{ CS42L42_RSENSE_CTL2, 0x00 },
124+
{ CS42L42_RSENSE_CTL3, 0x00 },
125+
{ CS42L42_TSENSE_CTL, 0x80 },
126+
{ CS42L42_HS_BIAS_CTL, 0xC0 },
127+
{ CS42L42_PWR_CTL1, 0x02 },
128+
{ CS42L42_ADC_OVFL_INT_MASK, 0xff },
129+
{ CS42L42_MIXER_INT_MASK, 0xff },
130+
{ CS42L42_SRC_INT_MASK, 0xff },
131+
{ CS42L42_ASP_RX_INT_MASK, 0xff },
132+
{ CS42L42_ASP_TX_INT_MASK, 0xff },
133+
{ CS42L42_CODEC_INT_MASK, 0xff },
134+
{ CS42L42_SRCPL_INT_MASK, 0xff },
135+
{ CS42L42_VPMON_INT_MASK, 0xff },
136+
{ CS42L42_PLL_LOCK_INT_MASK, 0xff },
137+
{ CS42L42_TSRS_PLUG_INT_MASK, 0xff },
138+
{ CS42L42_DET_INT1_MASK, 0xff },
139+
{ CS42L42_DET_INT2_MASK, 0xff },
140140
};
141141

142142
/* Vendor specific hw configuration for CS8409 */
@@ -282,115 +282,115 @@ const struct hda_pintbl dolphin_pincfgs[] = {
282282

283283
/* Vendor specific HW configuration for CS42L42 */
284284
static const struct cs8409_i2c_param dolphin_c0_init_reg_seq[] = {
285-
{ 0x1010, 0xB0 },
286-
{ 0x1D01, 0x00 },
285+
{ CS42L42_I2C_TIMEOUT, 0xB0 },
286+
{ CS42L42_ADC_CTL, 0x00 },
287287
{ 0x1D02, 0x06 },
288-
{ 0x1D03, 0x9F },
289-
{ 0x1107, 0x01 },
290-
{ 0x1009, 0x02 },
291-
{ 0x1007, 0x03 },
292-
{ 0x1201, 0x00 },
293-
{ 0x1208, 0x13 },
294-
{ 0x1205, 0xFF },
295-
{ 0x1206, 0x00 },
296-
{ 0x1207, 0x20 },
297-
{ 0x1202, 0x0D },
298-
{ 0x2A02, 0x02 },
299-
{ 0x2A03, 0x00 },
300-
{ 0x2A04, 0x00 },
301-
{ 0x2A05, 0x02 },
302-
{ 0x2A06, 0x00 },
303-
{ 0x2A07, 0x20 },
304-
{ 0x2A01, 0x0C },
305-
{ 0x2902, 0x01 },
306-
{ 0x2903, 0x02 },
307-
{ 0x2904, 0x00 },
308-
{ 0x2905, 0x00 },
309-
{ 0x2901, 0x01 },
310-
{ 0x1101, 0x0A },
311-
{ 0x1102, 0x84 },
312-
{ 0x2001, 0x03 },
313-
{ 0x2301, 0x3F },
314-
{ 0x2303, 0x3F },
315-
{ 0x2302, 0x3f },
316-
{ 0x1B75, 0xB6 },
317-
{ 0x1B73, 0xC2 },
318-
{ 0x1129, 0x01 },
319-
{ 0x1121, 0xF3 },
320-
{ 0x1103, 0x20 },
321-
{ 0x1105, 0x00 },
322-
{ 0x1112, 0x00 },
323-
{ 0x1113, 0x80 },
324-
{ 0x1C03, 0xC0 },
325-
{ 0x1101, 0x02 },
326-
{ 0x1316, 0xff },
327-
{ 0x1317, 0xff },
328-
{ 0x1318, 0xff },
329-
{ 0x1319, 0xff },
330-
{ 0x131a, 0xff },
331-
{ 0x131b, 0xff },
332-
{ 0x131c, 0xff },
333-
{ 0x131e, 0xff },
334-
{ 0x131f, 0xff },
335-
{ 0x1320, 0xff },
336-
{ 0x1b79, 0xff },
337-
{ 0x1b7a, 0xff }
288+
{ CS42L42_ADC_VOLUME, 0x9F },
289+
{ CS42L42_OSC_SWITCH, 0x01 },
290+
{ CS42L42_MCLK_CTL, 0x02 },
291+
{ CS42L42_SRC_CTL, 0x03 },
292+
{ CS42L42_MCLK_SRC_SEL, 0x00 },
293+
{ CS42L42_ASP_FRM_CFG, 0x13 },
294+
{ CS42L42_FSYNC_P_LOWER, 0xFF },
295+
{ CS42L42_FSYNC_P_UPPER, 0x00 },
296+
{ CS42L42_ASP_CLK_CFG, 0x20 },
297+
{ CS42L42_SPDIF_CLK_CFG, 0x0D },
298+
{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
299+
{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
300+
{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
301+
{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
302+
{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
303+
{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
304+
{ CS42L42_ASP_RX_DAI0_EN, 0x0C },
305+
{ CS42L42_ASP_TX_CH_EN, 0x01 },
306+
{ CS42L42_ASP_TX_CH_AP_RES, 0x02 },
307+
{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
308+
{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
309+
{ CS42L42_ASP_TX_SZ_EN, 0x01 },
310+
{ CS42L42_PWR_CTL1, 0x0A },
311+
{ CS42L42_PWR_CTL2, 0x84 },
312+
{ CS42L42_HP_CTL, 0x03 },
313+
{ CS42L42_MIXER_CHA_VOL, 0x3F },
314+
{ CS42L42_MIXER_CHB_VOL, 0x3F },
315+
{ CS42L42_MIXER_ADC_VOL, 0x3f },
316+
{ CS42L42_MIC_DET_CTL1, 0xB6 },
317+
{ CS42L42_TIPSENSE_CTL, 0xC2 },
318+
{ CS42L42_HS_CLAMP_DISABLE, 0x01 },
319+
{ CS42L42_HS_SWITCH_CTL, 0xF3 },
320+
{ CS42L42_PWR_CTL3, 0x20 },
321+
{ CS42L42_RSENSE_CTL2, 0x00 },
322+
{ CS42L42_RSENSE_CTL3, 0x00 },
323+
{ CS42L42_TSENSE_CTL, 0x80 },
324+
{ CS42L42_HS_BIAS_CTL, 0xC0 },
325+
{ CS42L42_PWR_CTL1, 0x02 },
326+
{ CS42L42_ADC_OVFL_INT_MASK, 0xff },
327+
{ CS42L42_MIXER_INT_MASK, 0xff },
328+
{ CS42L42_SRC_INT_MASK, 0xff },
329+
{ CS42L42_ASP_RX_INT_MASK, 0xff },
330+
{ CS42L42_ASP_TX_INT_MASK, 0xff },
331+
{ CS42L42_CODEC_INT_MASK, 0xff },
332+
{ CS42L42_SRCPL_INT_MASK, 0xff },
333+
{ CS42L42_VPMON_INT_MASK, 0xff },
334+
{ CS42L42_PLL_LOCK_INT_MASK, 0xff },
335+
{ CS42L42_TSRS_PLUG_INT_MASK, 0xff },
336+
{ CS42L42_DET_INT1_MASK, 0xff },
337+
{ CS42L42_DET_INT2_MASK, 0xff }
338338
};
339339

340340
static const struct cs8409_i2c_param dolphin_c1_init_reg_seq[] = {
341-
{ 0x1010, 0xB0 },
342-
{ 0x1D01, 0x00 },
341+
{ CS42L42_I2C_TIMEOUT, 0xB0 },
342+
{ CS42L42_ADC_CTL, 0x00 },
343343
{ 0x1D02, 0x06 },
344-
{ 0x1D03, 0x9F },
345-
{ 0x1107, 0x01 },
346-
{ 0x1009, 0x02 },
347-
{ 0x1007, 0x03 },
348-
{ 0x1201, 0x00 },
349-
{ 0x1208, 0x13 },
350-
{ 0x1205, 0xFF },
351-
{ 0x1206, 0x00 },
352-
{ 0x1207, 0x20 },
353-
{ 0x1202, 0x0D },
354-
{ 0x2A02, 0x02 },
355-
{ 0x2A03, 0x00 },
356-
{ 0x2A04, 0x80 },
357-
{ 0x2A05, 0x02 },
358-
{ 0x2A06, 0x00 },
359-
{ 0x2A07, 0xA0 },
360-
{ 0x2A01, 0x0C },
361-
{ 0x2902, 0x00 },
362-
{ 0x2903, 0x02 },
363-
{ 0x2904, 0x00 },
364-
{ 0x2905, 0x00 },
365-
{ 0x2901, 0x00 },
366-
{ 0x1101, 0x0E },
367-
{ 0x1102, 0x84 },
368-
{ 0x2001, 0x01 },
369-
{ 0x2301, 0x3F },
370-
{ 0x2303, 0x3F },
371-
{ 0x2302, 0x3f },
372-
{ 0x1B75, 0xB6 },
373-
{ 0x1B73, 0xC2 },
374-
{ 0x1129, 0x01 },
375-
{ 0x1121, 0xF3 },
376-
{ 0x1103, 0x20 },
377-
{ 0x1105, 0x00 },
378-
{ 0x1112, 0x00 },
379-
{ 0x1113, 0x80 },
380-
{ 0x1C03, 0xC0 },
381-
{ 0x1101, 0x06 },
382-
{ 0x1316, 0xff },
383-
{ 0x1317, 0xff },
384-
{ 0x1318, 0xff },
385-
{ 0x1319, 0xff },
386-
{ 0x131a, 0xff },
387-
{ 0x131b, 0xff },
388-
{ 0x131c, 0xff },
389-
{ 0x131e, 0xff },
390-
{ 0x131f, 0xff },
391-
{ 0x1320, 0xff },
392-
{ 0x1b79, 0xff },
393-
{ 0x1b7a, 0xff }
344+
{ CS42L42_ADC_VOLUME, 0x9F },
345+
{ CS42L42_OSC_SWITCH, 0x01 },
346+
{ CS42L42_MCLK_CTL, 0x02 },
347+
{ CS42L42_SRC_CTL, 0x03 },
348+
{ CS42L42_MCLK_SRC_SEL, 0x00 },
349+
{ CS42L42_ASP_FRM_CFG, 0x13 },
350+
{ CS42L42_FSYNC_P_LOWER, 0xFF },
351+
{ CS42L42_FSYNC_P_UPPER, 0x00 },
352+
{ CS42L42_ASP_CLK_CFG, 0x20 },
353+
{ CS42L42_SPDIF_CLK_CFG, 0x0D },
354+
{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
355+
{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
356+
{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x80 },
357+
{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
358+
{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
359+
{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0xA0 },
360+
{ CS42L42_ASP_RX_DAI0_EN, 0x0C },
361+
{ CS42L42_ASP_TX_CH_EN, 0x00 },
362+
{ CS42L42_ASP_TX_CH_AP_RES, 0x02 },
363+
{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
364+
{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
365+
{ CS42L42_ASP_TX_SZ_EN, 0x00 },
366+
{ CS42L42_PWR_CTL1, 0x0E },
367+
{ CS42L42_PWR_CTL2, 0x84 },
368+
{ CS42L42_HP_CTL, 0x01 },
369+
{ CS42L42_MIXER_CHA_VOL, 0x3F },
370+
{ CS42L42_MIXER_CHB_VOL, 0x3F },
371+
{ CS42L42_MIXER_ADC_VOL, 0x3f },
372+
{ CS42L42_MIC_DET_CTL1, 0xB6 },
373+
{ CS42L42_TIPSENSE_CTL, 0xC2 },
374+
{ CS42L42_HS_CLAMP_DISABLE, 0x01 },
375+
{ CS42L42_HS_SWITCH_CTL, 0xF3 },
376+
{ CS42L42_PWR_CTL3, 0x20 },
377+
{ CS42L42_RSENSE_CTL2, 0x00 },
378+
{ CS42L42_RSENSE_CTL3, 0x00 },
379+
{ CS42L42_TSENSE_CTL, 0x80 },
380+
{ CS42L42_HS_BIAS_CTL, 0xC0 },
381+
{ CS42L42_PWR_CTL1, 0x06 },
382+
{ CS42L42_ADC_OVFL_INT_MASK, 0xff },
383+
{ CS42L42_MIXER_INT_MASK, 0xff },
384+
{ CS42L42_SRC_INT_MASK, 0xff },
385+
{ CS42L42_ASP_RX_INT_MASK, 0xff },
386+
{ CS42L42_ASP_TX_INT_MASK, 0xff },
387+
{ CS42L42_CODEC_INT_MASK, 0xff },
388+
{ CS42L42_SRCPL_INT_MASK, 0xff },
389+
{ CS42L42_VPMON_INT_MASK, 0xff },
390+
{ CS42L42_PLL_LOCK_INT_MASK, 0xff },
391+
{ CS42L42_TSRS_PLUG_INT_MASK, 0xff },
392+
{ CS42L42_DET_INT1_MASK, 0xff },
393+
{ CS42L42_DET_INT2_MASK, 0xff }
394394
};
395395

396396
/* Vendor specific hw configuration for CS8409 */

0 commit comments

Comments
 (0)