|
119 | 119 | #define INT_UNMASK_ALL 0xFFFF |
120 | 120 | #define CHAN_ENABLE(chan) (0x101 << chan) |
121 | 121 | #define CHAN_DISABLE(chan) (0x100 << chan) |
| 122 | +#define CHAN_MASK(chan) (0x1 << chan) |
122 | 123 |
|
123 | 124 | #define DW_CFG_CH_SUSPEND 0x100 |
124 | 125 | #define DW_CFG_CH_FIFO_EMPTY 0x200 |
@@ -474,6 +475,31 @@ static int dw_dma_pause(struct dma *dma, int channel) |
474 | 475 | return 0; |
475 | 476 | } |
476 | 477 |
|
| 478 | +#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL |
| 479 | +static int dw_dma_stop(struct dma *dma, int channel) |
| 480 | +{ |
| 481 | + struct dma_pdata *p = dma_get_drvdata(dma); |
| 482 | + int ret = 0; |
| 483 | + uint32_t flags; |
| 484 | + uint32_t val = 0; |
| 485 | + |
| 486 | + spin_lock_irq(&dma->lock, flags); |
| 487 | + |
| 488 | + trace_dma("DDi"); |
| 489 | + |
| 490 | + ret = poll_for_register_delay(dma_base(dma) + DW_DMA_CHAN_EN, |
| 491 | + CHAN_MASK(channel), val, |
| 492 | + PLATFORM_DMA_TIMEOUT); |
| 493 | + if (ret < 0) |
| 494 | + trace_dma_error("esp"); |
| 495 | + |
| 496 | + dw_write(dma, DW_CLEAR_BLOCK, 0x1 << channel); |
| 497 | + p->chan[channel].status = COMP_STATE_PREPARE; |
| 498 | + |
| 499 | + spin_unlock_irq(&dma->lock, flags); |
| 500 | + return ret; |
| 501 | +} |
| 502 | +#else |
477 | 503 | static int dw_dma_stop(struct dma *dma, int channel) |
478 | 504 | { |
479 | 505 | struct dma_pdata *p = dma_get_drvdata(dma); |
@@ -508,6 +534,7 @@ static int dw_dma_stop(struct dma *dma, int channel) |
508 | 534 | spin_unlock_irq(&dma->lock, flags); |
509 | 535 | return ret; |
510 | 536 | } |
| 537 | +#endif |
511 | 538 |
|
512 | 539 | /* fill in "status" with current DMA channel state and position */ |
513 | 540 | static int dw_dma_status(struct dma *dma, int channel, |
|
0 commit comments