intel: ssp: handle TSRE and RSRE along with SSE

The current code does not follow recommended programming sequences:
TSRE and RSRE should be set before SSE and conversely cleared before
SSE.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Brent Lu <brent.lu@intel.com>

Author: plbossart

src/drivers/intel/ssp/ssp.c

@@ -285,8 +285,8 @@ static int ssp_set_config(struct dai *dai,
 	 */
 	sscr0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
 
-	/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */
-	sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL | SSCR1_RSRE | SSCR1_TSRE;
+	/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR, RSRE, TSRE */
+	sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL;
 
 	/* sscr2 dynamic setting is LJDFD */
 	sscr2 = SSCR2_SDFD | SSCR2_TURM1;
@@ -737,6 +737,12 @@ static int ssp_set_config(struct dai *dai,
 			ssp->clk_active |= SSP_CLK_BCLK_ES_REQ;
 
 			if (enable_sse) {
+
+				/* enable TRSE/RSRE before SSE */
+				ssp_update_bits(dai, SSCR1,
+						SSCR1_TSRE | SSCR1_RSRE,
+						SSCR1_TSRE | SSCR1_RSRE);
+
 				/* enable port */
 				ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
 
@@ -752,6 +758,11 @@ static int ssp_set_config(struct dai *dai,
 			dai_info(dai, "ssp_set_config(): hw_free stage: releasing BCLK clocks for SSP%d...",
 				 dai->index);
 			if (ssp->clk_active & SSP_CLK_BCLK_ACTIVE) {
+				/* clear TRSE/RSRE before SSE */
+				ssp_update_bits(dai, SSCR1,
+						SSCR1_TSRE | SSCR1_RSRE,
+						0);
+
 				ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
 				dai_info(dai, "ssp_set_config(): SSE clear for SSP%d", dai->index);
 			}
@@ -872,6 +883,11 @@ static void ssp_start(struct dai *dai, int direction)
 	ssp_pre_start(dai);
 
 	if (!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ)) {
+		/* enable TRSE/RSRE before SSE */
+		ssp_update_bits(dai, SSCR1,
+				SSCR1_TSRE | SSCR1_RSRE,
+				SSCR1_TSRE | SSCR1_RSRE);
+
 		/* enable port */
 		ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
 		dai_info(dai, "ssp_start(): SSE set for SSP%d", dai->index);
@@ -889,13 +905,10 @@ static void ssp_start(struct dai *dai, int direction)
 	}
 
 	/* enable DMA */
-	if (direction == DAI_DIR_PLAYBACK) {
-		ssp_update_bits(dai, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
+	if (direction == DAI_DIR_PLAYBACK)
 		ssp_update_bits(dai, SSTSA, SSTSA_TXEN, SSTSA_TXEN);
-	} else {
-		ssp_update_bits(dai, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
+	else
 		ssp_update_bits(dai, SSRSA, SSRSA_RXEN, SSRSA_RXEN);
-	}
 
 	/* wait to get valid fifo status */
 	wait_delay(PLATFORM_SSP_DELAY);
@@ -916,7 +929,6 @@ static void ssp_stop(struct dai *dai, int direction)
 	/* stop Rx if neeed */
 	if (direction == DAI_DIR_CAPTURE &&
 	    ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_PREPARE) {
-		ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0);
 		ssp_update_bits(dai, SSRSA, SSRSA_RXEN, 0);
 		ssp_empty_rx_fifo(dai);
 		ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE;
@@ -927,7 +939,6 @@ static void ssp_stop(struct dai *dai, int direction)
 	if (direction == DAI_DIR_PLAYBACK &&
 	    ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_PREPARE) {
 		ssp_empty_tx_fifo(dai);
-		ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0);
 		ssp_update_bits(dai, SSTSA, SSTSA_TXEN, 0);
 		ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE;
 		dai_info(dai, "ssp_stop(), TX stop");
@@ -937,6 +948,11 @@ static void ssp_stop(struct dai *dai, int direction)
 	if (ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_PREPARE &&
 	    ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_PREPARE) {
 		if (!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ)) {
+			/* clear TRSE/RSRE before SSE */
+			ssp_update_bits(dai, SSCR1,
+					SSCR1_TSRE | SSCR1_RSRE,
+					0);
+
 			ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
 			dai_info(dai, "ssp_stop(): SSE clear SSP%d", dai->index);
 		}