DMIC: Enable power for DMIC for ICL platform.

Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>

Author: mrajwa

src/drivers/intel/cavs/dmic.c

@@ -1450,6 +1450,8 @@ static int dmic_probe(struct dai *dai)
 	if (dai_get_drvdata(dai))
 		return -EEXIST; /* already created */
 
+	/* Enable DMIC power */
+	pm_runtime_get_sync(DMIC_POW, dai->index);
 	/* Disable dynamic clock gating for dmic before touching any reg */
 	pm_runtime_get_sync(DMIC_CLK, dai->index);
 
@@ -1482,6 +1484,8 @@ static int dmic_remove(struct dai *dai)
 	interrupt_unregister(dmic_irq(dai));
 
 	pm_runtime_put_sync(DMIC_CLK, dai->index);
+	/* Disable DMIC power */
+	pm_runtime_put_sync(DMIC_POW, dai->index);
 
 	rfree(dma_get_drvdata(dai));
 	dai_set_drvdata(dai, NULL);

src/include/sof/pm_runtime.h

@@ -62,6 +62,7 @@ enum pm_runtime_context {
 	PM_RUNTIME_HOST_DMA_L1 = 0,	/**< Host DMA L1 Exit */
 	SSP_CLK,			/**< SSP Clock */
 	DMIC_CLK,			/**< DMIC Clock */
+	DMIC_POW,			/**< DMIC Power */
 	DW_DMAC_CLK			/**< DW DMAC Clock */
 };
 

src/platform/cannonlake/include/platform/memory.h

@@ -42,6 +42,11 @@
 #define SHIM_BASE		0x00071F00
 #define SHIM_SIZE		0x00000100
 
+/* Digital Mic Shim Registers */
+#define DMIC_SHIM_BASE	0x00071E80
+#define DMICLCTL_OFFSET 0x04
+#define DMICLCTL	(DMIC_SHIM_BASE + DMICLCTL_OFFSET)
+
 /* cmd IO to audio codecs */
 #define CMD_BASE		0x00001100
 #define CMD_SIZE		0x00000010

src/platform/cannonlake/include/platform/shim.h

@@ -233,6 +233,9 @@
 #define DMWBA_ENABLE		(1 << 0)
 #define DMWBA_READONLY		(1 << 1)
 
+/* DMIC power ON bit */
+#define DMICLCTL_SPA	((uint32_t) BIT(0))
+
 #ifndef ASSEMBLY
 
 static inline uint16_t shim_read16(uint16_t reg)

src/platform/icelake/include/platform/memory.h

@@ -42,6 +42,11 @@
 #define SHIM_BASE		0x00071F00
 #define SHIM_SIZE		0x00000100
 
+/* Digital Mic Shim Registers */
+#define DMIC_SHIM_BASE	0x00071E80
+#define DMICLCTL_OFFSET 0x04
+#define DMICLCTL	(DMIC_SHIM_BASE + DMICLCTL_OFFSET)
+
 /* cmd IO to audio codecs */
 #define CMD_BASE		0x00001100
 #define CMD_SIZE		0x00000010

src/platform/icelake/include/platform/shim.h

@@ -233,6 +233,9 @@
 #define DMWBA_ENABLE		(1 << 0)
 #define DMWBA_READONLY		(1 << 1)
 
+/* DMIC power ON bit */
+#define DMICLCTL_SPA	((uint32_t) BIT(0))
+
 #ifndef ASSEMBLY
 
 static inline uint16_t shim_read16(uint16_t reg)

src/platform/intel/cavs/pm_runtime.c

@@ -123,7 +123,27 @@ static inline void cavs_pm_runtime_en_dmic_clk_gating(uint32_t index)
 		    index, shim_read(SHIM_CLKCTL));
 #endif
 }
+static inline void cavs_pm_runtime_en_dmic_power(uint32_t index)
+{
+	(void) index;
+#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \
+	|| defined(CONFIG_SUECREEK)
+	/* Enable DMIC power */
+	io_reg_write(DMICLCTL,
+		    (io_reg_read(DMICLCTL) | DMICLCTL_SPA));
+#endif
+}
+static inline void cavs_pm_runtime_dis_dmic_power(uint32_t index)
+{
+	(void) index;
+#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \
+	|| defined(CONFIG_SUECREEK)
+	/* Disable DMIC power */
+	io_reg_write(DMICLCTL,
+		    (io_reg_read(DMICLCTL) & (~DMICLCTL_SPA)));
 #endif
+}
+#endif /* #if defined(CONFIG_DMIC) */
 
 static inline void cavs_pm_runtime_dis_dwdma_clk_gating(uint32_t index)
 {
@@ -171,6 +191,9 @@ void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index,
 	case DMIC_CLK:
 		cavs_pm_runtime_dis_dmic_clk_gating(index);
 		break;
+	case DMIC_POW:
+		cavs_pm_runtime_en_dmic_power(index);
+		break;
 #endif
 	case DW_DMAC_CLK:
 		cavs_pm_runtime_dis_dwdma_clk_gating(index);
@@ -194,6 +217,9 @@ void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index,
 	case DMIC_CLK:
 		cavs_pm_runtime_en_dmic_clk_gating(index);
 		break;
+	case DMIC_POW:
+		cavs_pm_runtime_dis_dmic_power(index);
+		break;
 #endif
 	case DW_DMAC_CLK:
 		cavs_pm_runtime_en_dwdma_clk_gating(index);

src/platform/suecreek/include/platform/memory.h

@@ -42,6 +42,11 @@
 #define SHIM_BASE		0x00071F00
 #define SHIM_SIZE		0x00000100
 
+/* Digital Mic Shim Registers */
+#define DMIC_SHIM_BASE	0x00071E80
+#define DMICLCTL_OFFSET 0x04
+#define DMICLCTL	(DMIC_SHIM_BASE + DMICLCTL_OFFSET)
+
 /* cmd IO to audio codecs */
 #define CMD_BASE		0x00001100
 #define CMD_SIZE		0x00000010

src/platform/suecreek/include/platform/shim.h

@@ -233,6 +233,9 @@
 #define DMWBA_ENABLE		(1 << 0)
 #define DMWBA_READONLY		(1 << 1)
 
+/* DMIC power ON bit */
+#define DMICLCTL_SPA	((uint32_t) BIT(0))
+
 #ifndef ASSEMBLY
 
 static inline uint16_t shim_read16(uint16_t reg)