Commit 4a9bce7
west.yml: update zephyr to 05a3f62f445
Total of 1145 commits.
Changes include:
a5a9ff4c28c xtensa: handle instruction TLB multi-hit exception
9b9e9ebde77 xtensa: mmu: data TLB multi-hit only handle
exception address
599df95875c xtensa: return back to interrupted thread for
certain exceptions
27e48026215 xtensa: remove unnecessary setting of is_fatal_error
during exc
8d072e85b1e ipc: intel_adsp: fix inverted sync wait condition
ed4cec2d220 xtensa: ptables: doxygen doc
744a7f4daf1 xtensa: mmu: do doxygen for functions
50e980d9a83 xtensa: mmu: halt system if not enough L2 tables
during boot
82b7d94d452 xtensa: mmu: add debug logs on page table
allocations
0777dbea028 xtensa: mmu: assert when L2 table allocation fails
during dup
71262d0e075 arch: xtensa: avoid the use of "sanity check" term
Signed-off-by: Daniel Leung <daniel.leung@intel.com>1 parent 15f94f6 commit 4a9bce7
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