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Platform: Add ACP 7.0 platform support for native zephyr
This commit adds support for ACP 7.0 native zephyr and also adds acp_7_0 in zephyr build script. Changes include: - Add changes in platform-specific files for ACP 7.0 for native zephyr support - Add ACP 7.0 in cmakelist under zephyr - Remove DMA based scheduling from kconfig for ACP 7.0 - Add acp_7_0 support in zephyr build script - Add xtensa files idma.h,xtensa-types.h and xt_externalregisters.h - Add UINT32_C macro fallback for stdint.h compatibility in tie.h - Replace addi.a with addi in tie-asm.h for Xtensa assembler compatibility. This enables native Zephyr-based SOF support for AMD ACP 7.0 hardware platform. Signed-off-by: Sivasubramanian <sravisar@amd.com>
1 parent 9ee2d5d commit 4e69786

19 files changed

Lines changed: 4525 additions & 79 deletions

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‎app/boards/acp_7_0_adsp.conf‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
CONFIG_ACP_7_0=y
2+
CONFIG_HAVE_AGENT=n
3+
CONFIG_DCACHE_LINE_SIZE_DETECT=n
4+
CONFIG_DCACHE_LINE_SIZE=128
5+
CONFIG_DYNAMIC_INTERRUPTS=y
6+
CONFIG_SHARED_INTERRUPTS=n
7+
CONFIG_ZEPHYR_LOG=n
8+
CONFIG_DMA=y
9+
CONFIG_DMA_DOMAIN=n
10+
CONFIG_ZEPHYR_NATIVE_DRIVERS=y
11+
CONFIG_AMS=n
12+
CONFIG_WRAP_ACTUAL_POSITION=y
13+
CONFIG_TRACE=n
14+
CONFIG_COMP_VOLUME=y
15+
CONFIG_COMP_SRC=n
16+
CONFIG_COMP_FIR=n
17+
CONFIG_COMP_IIR=n
18+
CONFIG_COMP_DCBLOCK=n
19+
CONFIG_COMP_CROSSOVER=n
20+
CONFIG_COMP_DRC=n
21+
CONFIG_COMP_MULTIBAND_DRC=n
22+
CONFIG_COMP_TONE=n
23+
CONFIG_COMP_KPB=n
24+
CONFIG_MAXIM_DSM=n
25+
CONFIG_COMP_ASRC=n
26+
CONFIG_COMP_IGO_NR=n
27+
CONFIG_COMP_COPIER=n
28+
CONFIG_COMP_RTNR=n
29+
CONFIG_COMP_ARIA=n
30+
CONFIG_COMP_BASEFW_IPC4=n
31+
CONFIG_COMP_UP_DOWN_MIXER=n
32+
CONFIG_COMP_TDFB=n
33+
CONFIG_COMP_SEL=n
34+
CONFIG_COMP_MIXER=n
35+
CONFIG_ASRC_SUPPORT_CONVERSION_24000_TO_08000=n
36+
CONFIG_ASRC_SUPPORT_CONVERSION_24000_TO_16000=n
37+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_08000=n
38+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_11025=n
39+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_12000=n
40+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_16000=n
41+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_22050=n
42+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_24000=n
43+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_32000=n
44+
CONFIG_ASRC_SUPPORT_CONVERSION_48000_TO_44100=n
45+
CONFIG_CORE_COUNT=1
46+
CONFIG_FORMAT_CONVERT_HIFI3=n

‎scripts/xtensa-build-zephyr.py‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,12 @@ class PlatformConfig:
123123
"rmb_LX7_HiFi5_PROD",
124124
RIMAGE_KEY = "key param ignored by acp_6_0"
125125
),
126+
"acp_7_0" : PlatformConfig(
127+
"amd", "acp_7_0_adsp/acp_7_0",
128+
f"RI-2023.11{xtensa_tools_version_postfix}",
129+
"ACP_7_0_HiFi5_NNE_PROD",
130+
RIMAGE_KEY = "key param ignored by acp_7_0"
131+
),
126132
# MediaTek platforms
127133
# (move to platform_configs_all on next Zephyr SDK release after 0.17.0)
128134
"mt8195" : PlatformConfig(
@@ -1306,7 +1312,7 @@ def gzip_compress(fname, gzdst=None):
13061312
RI_INFO_UNSUPPORTED = []
13071313

13081314
RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8ulp', 'imx95']
1309-
RI_INFO_UNSUPPORTED += ['rn', 'acp_6_0']
1315+
RI_INFO_UNSUPPORTED += ['acp_6_0','acp_7_0']
13101316
RI_INFO_UNSUPPORTED += ['mt8186', 'mt8188', 'mt8195', 'mt8196', 'mt8365']
13111317
RI_INFO_UNSUPPORTED += ['qemu_xtensa', 'qemu_xtensa_mmu']
13121318

‎src/drivers/amd/common/ipc.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
11
// SPDX-License-Identifier: BSD-3-Clause
22
//
3-
//Copyright(c) 2023 AMD. All rights reserved.
3+
//Copyright(c) 2023, 2026 AMD. All rights reserved.
44
//
55
//Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
66
// SaiSurya, Ch <saisurya.chakkaveeravenkatanaga@amd.com>
7+
// Sivasubramanian <sravisar@amd.com>
78

89
#include <rtos/panic.h>
9-
#include <platform/chip_offset_byte.h>
10-
#include <platform/chip_registers.h>
1110
#include <rtos/interrupt.h>
1211
#include <sof/ipc/driver.h>
1312
#include <sof/ipc/msg.h>
@@ -91,7 +90,7 @@ int platform_ipc_init(struct ipc *ipc)
9190
/* schedule */
9291
schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_amd_uuid),
9392
&ipc_task_ops, ipc, 0, 0);
94-
arch_interrupt_clear(IRQ_NUM_EXT_LEVEL3);
93+
interrupt_disable(IRQ_NUM_EXT_LEVEL3, ipc);
9594
interrupt_register(IRQ_NUM_EXT_LEVEL3, amd_irq_handler, ipc);
9695
/* Enabling software interuppts */
9796
interrupt_enable(IRQ_NUM_EXT_LEVEL3, ipc);

‎src/drivers/amd/rembrandt/ipc.c‎

Lines changed: 32 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,11 @@
11
// SPDX-License-Identifier: BSD-3-Clause
22
//
3-
//Copyright(c) 2022 AMD. All rights reserved.
3+
//Copyright(c) 2022, 2026 AMD. All rights reserved.
44
//
55
//Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
66
// Bala Kishore <balakishore.pati@amd.com>
7-
7+
// Sivasubramanian <sravisar@amd.com>
88
#include <rtos/panic.h>
9-
#include <platform/chip_offset_byte.h>
10-
#include <platform/chip_registers.h>
119
#include <rtos/interrupt.h>
1210
#include <sof/ipc/driver.h>
1311
#include <sof/ipc/msg.h>
@@ -32,9 +30,39 @@
3230
#include <platform/platform.h>
3331
#include <platform/ipc.h>
3432

33+
#define HOST_TO_DSP_INTR 1
34+
#define INTERRUPT_DISABLE 0
35+
LOG_MODULE_REGISTER(ipc1, CONFIG_SOF_LOG_LEVEL);
3536
volatile acp_scratch_mem_config_t *pscratch_mem_cfg = (volatile acp_scratch_mem_config_t *)
3637
(PU_SCRATCH_REG_BASE + SCRATCH_REG_OFFSET);
3738

39+
#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
40+
/* Clear the Acknowledge ( status) for the host to DSP interrupt */
41+
void acp_ack_intr_from_host(void)
42+
{
43+
/* acknowledge the host interrupt */
44+
acp_dsp_sw_intr_stat_t sw_intr_stat;
45+
46+
sw_intr_stat.u32all = 0;
47+
sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE;
48+
io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all);
49+
}
50+
51+
/* This function triggers a host interrupt from ACP DSP */
52+
void acp_dsp_to_host_intr_trig(void)
53+
{
54+
acp_sw_intr_trig_t sw_intr_trig;
55+
56+
/* Read the Software Interrupt controller register and update */
57+
sw_intr_trig = (acp_sw_intr_trig_t)io_reg_read(PU_REGISTER_BASE +
58+
ACP_SW_INTR_TRIG);
59+
/* Configures the trigger bit in ACP_DSP_SW_INTR_TRIG register */
60+
sw_intr_trig.bits.trig_dsp0_to_host_intr = INTERRUPT_ENABLE;
61+
/* Write the Software Interrupt controller register */
62+
io_reg_write((PU_REGISTER_BASE + ACP_SW_INTR_TRIG), sw_intr_trig.u32all);
63+
}
64+
#endif /* CONFIG_ZEPHYR_NATIVE_DRIVERS */
65+
3866
void amd_irq_handler(void *arg)
3967
{
4068
struct ipc *ipc = arg;

‎src/platform/Kconfig‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -238,8 +238,6 @@ config ACP_7_0
238238
select XT_INTERRUPT_LEVEL_4
239239
select XT_WAITI_DELAY
240240
select XTENSA_EXCLUSIVE
241-
select AMD
242-
select SCHEDULE_DMA_MULTI_CHANNEL
243241
help
244242
Select if your target platform is acp_7_0-compatible
245243

‎src/platform/amd/acp_7_0/include/arch/xtensa/config/tie-asm.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@
182182
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
183183
xchal_sa_align \ptr, 0, 0, 16, 16
184184
ae_s64.i aed0, \ptr, .Lxchal_ofs_+56
185-
addi.a \ptr, \ptr, 64
185+
addi \ptr, \ptr, 64
186186
ae_s64.i aed1, \ptr, .Lxchal_ofs_+0
187187
ae_s64.i aed2, \ptr, .Lxchal_ofs_+8
188188
ae_s64.i aed3, \ptr, .Lxchal_ofs_+16
@@ -191,7 +191,7 @@
191191
ae_s64.i aed6, \ptr, .Lxchal_ofs_+40
192192
ae_s64.i aed7, \ptr, .Lxchal_ofs_+48
193193
ae_s64.i aed8, \ptr, .Lxchal_ofs_+56
194-
addi.a \ptr, \ptr, 64
194+
addi \ptr, \ptr, 64
195195
ae_s64.i aed9, \ptr, .Lxchal_ofs_+0
196196
ae_s64.i aed10, \ptr, .Lxchal_ofs_+8
197197
ae_s64.i aed11, \ptr, .Lxchal_ofs_+16
@@ -200,7 +200,7 @@
200200
ae_s64.i aed14, \ptr, .Lxchal_ofs_+40
201201
ae_s64.i aed15, \ptr, .Lxchal_ofs_+48
202202
ae_s64.i aed16, \ptr, .Lxchal_ofs_+56
203-
addi.a \ptr, \ptr, 64
203+
addi \ptr, \ptr, 64
204204
ae_s64.i aed17, \ptr, .Lxchal_ofs_+0
205205
ae_s64.i aed18, \ptr, .Lxchal_ofs_+8
206206
ae_s64.i aed19, \ptr, .Lxchal_ofs_+16
@@ -209,7 +209,7 @@
209209
ae_s64.i aed22, \ptr, .Lxchal_ofs_+40
210210
ae_s64.i aed23, \ptr, .Lxchal_ofs_+48
211211
ae_s64.i aed24, \ptr, .Lxchal_ofs_+56
212-
addi.a \ptr, \ptr, 64
212+
addi \ptr, \ptr, 64
213213
ae_s64.i aed25, \ptr, .Lxchal_ofs_+0
214214
ae_s64.i aed26, \ptr, .Lxchal_ofs_+8
215215
ae_s64.i aed27, \ptr, .Lxchal_ofs_+16
@@ -225,12 +225,12 @@
225225
s8i \at1, \ptr, .Lxchal_ofs_+58
226226
ae_movae \at1, aep3
227227
s8i \at1, \ptr, .Lxchal_ofs_+59
228-
addi.a \ptr, \ptr, 64
228+
addi \ptr, \ptr, 64
229229
ae_salign128.i u0, \ptr, .Lxchal_ofs_+0
230230
ae_salign128.i u1, \ptr, .Lxchal_ofs_+16
231231
ae_salign128.i u2, \ptr, .Lxchal_ofs_+32
232232
ae_salign128.i u3, \ptr, .Lxchal_ofs_+48
233-
addi.a \ptr, \ptr, -320
233+
addi \ptr, \ptr, -320
234234
ae_movdrzbvc aed0 // ureg AE_ZBIASV8C
235235
ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0
236236
ae_movvfcrfsr aed0 // ureg FCR_FSR
@@ -302,7 +302,7 @@
302302
l32i \at1, \ptr, .Lxchal_ofs_+52
303303
wur.ae_cend2 \at1 // ureg 251
304304
ae_l64.i aed0, \ptr, .Lxchal_ofs_+56
305-
addi.a \ptr, \ptr, 64
305+
addi \ptr, \ptr, 64
306306
ae_l64.i aed1, \ptr, .Lxchal_ofs_+0
307307
ae_l64.i aed2, \ptr, .Lxchal_ofs_+8
308308
ae_l64.i aed3, \ptr, .Lxchal_ofs_+16
@@ -311,7 +311,7 @@
311311
ae_l64.i aed6, \ptr, .Lxchal_ofs_+40
312312
ae_l64.i aed7, \ptr, .Lxchal_ofs_+48
313313
ae_l64.i aed8, \ptr, .Lxchal_ofs_+56
314-
addi.a \ptr, \ptr, 64
314+
addi \ptr, \ptr, 64
315315
ae_l64.i aed9, \ptr, .Lxchal_ofs_+0
316316
ae_l64.i aed10, \ptr, .Lxchal_ofs_+8
317317
ae_l64.i aed11, \ptr, .Lxchal_ofs_+16
@@ -320,7 +320,7 @@
320320
ae_l64.i aed14, \ptr, .Lxchal_ofs_+40
321321
ae_l64.i aed15, \ptr, .Lxchal_ofs_+48
322322
ae_l64.i aed16, \ptr, .Lxchal_ofs_+56
323-
addi.a \ptr, \ptr, 64
323+
addi \ptr, \ptr, 64
324324
ae_l64.i aed17, \ptr, .Lxchal_ofs_+0
325325
ae_l64.i aed18, \ptr, .Lxchal_ofs_+8
326326
ae_l64.i aed19, \ptr, .Lxchal_ofs_+16
@@ -329,15 +329,15 @@
329329
ae_l64.i aed22, \ptr, .Lxchal_ofs_+40
330330
ae_l64.i aed23, \ptr, .Lxchal_ofs_+48
331331
ae_l64.i aed24, \ptr, .Lxchal_ofs_+56
332-
addi.a \ptr, \ptr, 64
332+
addi \ptr, \ptr, 64
333333
ae_l64.i aed25, \ptr, .Lxchal_ofs_+0
334334
ae_l64.i aed26, \ptr, .Lxchal_ofs_+8
335335
ae_l64.i aed27, \ptr, .Lxchal_ofs_+16
336336
ae_l64.i aed28, \ptr, .Lxchal_ofs_+24
337337
ae_l64.i aed29, \ptr, .Lxchal_ofs_+32
338338
ae_l64.i aed30, \ptr, .Lxchal_ofs_+40
339339
ae_l64.i aed31, \ptr, .Lxchal_ofs_+48
340-
addi.a \ptr, \ptr, 56
340+
addi \ptr, \ptr, 56
341341
l8ui \at1, \ptr, .Lxchal_ofs_+0
342342
ae_movea aep0, \at1
343343
l8ui \at1, \ptr, .Lxchal_ofs_+1
@@ -346,7 +346,7 @@
346346
ae_movea aep2, \at1
347347
l8ui \at1, \ptr, .Lxchal_ofs_+3
348348
ae_movea aep3, \at1
349-
addi.a \ptr, \ptr, 8
349+
addi \ptr, \ptr, 8
350350
ae_lalign128.i u0, \ptr, .Lxchal_ofs_+0
351351
ae_lalign128.i u1, \ptr, .Lxchal_ofs_+16
352352
ae_lalign128.i u2, \ptr, .Lxchal_ofs_+32

‎src/platform/amd/acp_7_0/include/arch/xtensa/config/tie.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@
3232
#ifndef XTENSA_CORE_TIE_H
3333
#define XTENSA_CORE_TIE_H
3434

35+
#ifndef UINT32_C
36+
#define UINT32_C(x) x
37+
#endif
38+
3539
/* parasoft-begin-suppress ALL "This file not MISRA checked." */
3640

3741
#define XCHAL_CP_NUM UINT32_C(1) /* number of coprocessors */

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