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platform: mtk: add mt8365 memory layout and register definitions
Add memory layout and register addresses for mt8365. [Cache] I-Cache: 32KB, 4-way Associativity D-Cache: 32KB, 4-way Associativity [Memory] DRAM: DSP can access DRAM shared with CPU Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
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‎src/platform/mt8365/include/platform/drivers/mt_reg_base.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Andrew Perepech <andrew.perepech@mediatek.com>
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*/
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#ifndef MT_REG_BASE_H
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#define MT_REG_BASE_H
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#define DSP_REG_BASE (0x1D062000) /* DSPCFG base */
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#define DSP_TIMER_BASE (0x1D060000)
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#define DSP_UART0_BASE (0x1D061000)
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#define DSP_WDT_BASE (0x1D062400)
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#define DSP_IRQ_BASE (0x1D063000)
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#define DSP_D_TCM (CFG_HIFI4_DTCM_ADDRESS)
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#define DSP_I_TCM (CFG_HIFI4_ITCM_ADDRESS)
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#define DSP_DRAM_BASE (CFG_HIFI4_DRAM_ADDRESS)
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#define DSP_AUDIO_SRAM_BASE (0x11221000)
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#define DSP_AUDIO_SRAM_SIZE (0xA000)
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#define DSP_REG_REMAP_BASE (0x1D060000)
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#define DSP_REG_REMAP_SIZE (0x8000)
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#define DSP_SYS_REG_BASE (0x10000000)
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#define DSP_SYS_REG_SIZE (0x1221000)
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#define DSP_VER_REG_BASE (0x08000000)
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#define DSP_VER_REG_SIZE (0x1000)
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#define DSP_JTAGMUX (DSP_REG_BASE + 0x0000)
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#define DSP_ALTRESETVEC (DSP_REG_BASE + 0x0004)
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#define DSP_PDEBUGDATA (DSP_REG_BASE + 0x0008)
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#define DSP_PDEBUGBUS0 (DSP_REG_BASE + 0x000c)
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#define DSP_PDEBUGBUS1 (DSP_REG_BASE + 0x0010)
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#define DSP_PDEBUGINST (DSP_REG_BASE + 0x0014)
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#define DSP_PDEBUGLS0STAT (DSP_REG_BASE + 0x0018)
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#define DSP_PDEBUGLS1STAT (DSP_REG_BASE + 0x001c)
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#define DSP_PDEBUGPC (DSP_REG_BASE + 0x0020)
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#define DSP_RESET_SW (DSP_REG_BASE + 0x0024)
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#define DSP_PFAULTBUS (DSP_REG_BASE + 0x0028)
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#define DSP_PFAULTINFO (DSP_REG_BASE + 0x002c)
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#define DSP_GPR00 (DSP_REG_BASE + 0x0030)
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#define DSP_GPR01 (DSP_REG_BASE + 0x0034)
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#define DSP_GPR02 (DSP_REG_BASE + 0x0038)
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#define DSP_GPR03 (DSP_REG_BASE + 0x003c)
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#define DSP_GPR04 (DSP_REG_BASE + 0x0040)
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#define DSP_GPR05 (DSP_REG_BASE + 0x0044)
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#define DSP_GPR06 (DSP_REG_BASE + 0x0048)
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#define DSP_GPR07 (DSP_REG_BASE + 0x004c)
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#define DSP_GPR08 (DSP_REG_BASE + 0x0050)
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#define DSP_GPR09 (DSP_REG_BASE + 0x0054)
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#define DSP_GPR0A (DSP_REG_BASE + 0x0058)
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#define DSP_GPR0B (DSP_REG_BASE + 0x005c)
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#define DSP_GPR0C (DSP_REG_BASE + 0x0060)
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#define DSP_GPR0D (DSP_REG_BASE + 0x0064)
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#define DSP_GPR0E (DSP_REG_BASE + 0x0068)
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#define DSP_GPR0F (DSP_REG_BASE + 0x006c)
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#define DSP_GPR10 (DSP_REG_BASE + 0x0070)
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#define DSP_GPR11 (DSP_REG_BASE + 0x0074)
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#define DSP_GPR12 (DSP_REG_BASE + 0x0078)
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#define DSP_GPR13 (DSP_REG_BASE + 0x007c)
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#define DSP_GPR14 (DSP_REG_BASE + 0x0080)
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#define DSP_GPR15 (DSP_REG_BASE + 0x0084)
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#define DSP_GPR16 (DSP_REG_BASE + 0x0088)
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#define DSP_GPR17 (DSP_REG_BASE + 0x008c)
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#define DSP_GPR18 (DSP_REG_BASE + 0x0090)
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#define DSP_GPR19 (DSP_REG_BASE + 0x0094)
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#define DSP_GPR1A (DSP_REG_BASE + 0x0098)
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#define DSP_GPR1B (DSP_REG_BASE + 0x009c)
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#define DSP_GPR1C (DSP_REG_BASE + 0x00a0)
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#define DSP_GPR1D (DSP_REG_BASE + 0x00a4)
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#define DSP_GPR1E (DSP_REG_BASE + 0x00a8)
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#define DSP_GPR1F (DSP_REG_BASE + 0x00ac)
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#define DSP_TCM_OFFSET (DSP_REG_BASE + 0x00b0) /* not used */
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#define DSP_DDR_OFFSET (DSP_REG_BASE + 0x00b4) /* not used */
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#define DSP_INTFDSP (DSP_REG_BASE + 0x00d0)
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#define DSP_INTFDSP_CLR (DSP_REG_BASE + 0x00d4)
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#define DSP_SRAM_PD_SW1 (DSP_REG_BASE + 0x00d8)
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#define DSP_SRAM_PD_SW2 (DSP_REG_BASE + 0x00dc)
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#define DSP_OCD (DSP_REG_BASE + 0x00e0)
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#define DSP_RG_DSP_IRQ_POL (DSP_REG_BASE + 0x00f0) /* not used */
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#define DSP_DSP_IRQ_EN (DSP_REG_BASE + 0x00f4) /* not used */
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#define DSP_DSP_IRQ_LEVEL (DSP_REG_BASE + 0x00f8) /* not used */
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#define DSP_DSP_IRQ_STATUS (DSP_REG_BASE + 0x00fc) /* not used */
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#define DSP_RG_INT2CIRQ (DSP_REG_BASE + 0x0114)
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#define DSP_RG_INT_POL_CTL0 (DSP_REG_BASE + 0x0120)
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#define DSP_RG_INT_EN_CTL0 (DSP_REG_BASE + 0x0130)
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#define DSP_RG_INT_LV_CTL0 (DSP_REG_BASE + 0x0140)
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#define DSP_RG_INT_STATUS0 (DSP_REG_BASE + 0x0150)
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#define DSP_PDEBUGSTATUS0 (DSP_REG_BASE + 0x0200)
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#define DSP_PDEBUGSTATUS1 (DSP_REG_BASE + 0x0204)
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#define DSP_PDEBUGSTATUS2 (DSP_REG_BASE + 0x0208)
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#define DSP_PDEBUGSTATUS3 (DSP_REG_BASE + 0x020c)
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#define DSP_PDEBUGSTATUS4 (DSP_REG_BASE + 0x0210)
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#define DSP_PDEBUGSTATUS5 (DSP_REG_BASE + 0x0214)
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#define DSP_PDEBUGSTATUS6 (DSP_REG_BASE + 0x0218)
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#define DSP_PDEBUGSTATUS7 (DSP_REG_BASE + 0x021c)
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#define DSP_DSP2PSRAM_PRIORITY (DSP_REG_BASE + 0x0220) /* not used */
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#define DSP_AUDIO_DSP2SPM_INT (DSP_REG_BASE + 0x0224)
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#define DSP_AUDIO_DSP2SPM_INT_ACK (DSP_REG_BASE + 0x0228)
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#define DSP_AUDIO_DSP_DEBUG_SEL (DSP_REG_BASE + 0x022C)
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#define DSP_AUDIO_DSP_EMI_BASE_ADDR (DSP_REG_BASE + 0x02E0) /* not used */
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#define DSP_AUDIO_DSP_SHARED_IRAM (DSP_REG_BASE + 0x02E4)
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#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON (DSP_REG_BASE + 0x02F0)
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#define DSP_RG_SEMAPHORE00 (DSP_REG_BASE + 0x0300)
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#define DSP_RG_SEMAPHORE01 (DSP_REG_BASE + 0x0304)
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#define DSP_RG_SEMAPHORE02 (DSP_REG_BASE + 0x0308)
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#define DSP_RG_SEMAPHORE03 (DSP_REG_BASE + 0x030C)
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#define DSP_RG_SEMAPHORE04 (DSP_REG_BASE + 0x0310)
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#define DSP_RG_SEMAPHORE05 (DSP_REG_BASE + 0x0314)
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#define DSP_RG_SEMAPHORE06 (DSP_REG_BASE + 0x0318)
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#define DSP_RG_SEMAPHORE07 (DSP_REG_BASE + 0x031C)
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#define DSP_RESERVED_0 (DSP_REG_BASE + 0x03F0)
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#define DSP_RESERVED_1 (DSP_REG_BASE + 0x03F4) /* use for tickless status */
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/* Redefinition for using Special registers */
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#define TICKLESS_STATUS_REG (DSP_RESERVED_1)
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/* WDT CONFIGS */
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#define ADSP_WDT_MODE (DSP_REG_BASE + 0x400 + 0x00)
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#define ADSP_WDT_LENGTH (DSP_REG_BASE + 0x400 + 0x04)
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#define ADSP_WDT_RESTART (DSP_REG_BASE + 0x400 + 0x08)
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#define ADSP_WDT_STA (DSP_REG_BASE + 0x400 + 0x0C)
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#define ADSP_WDT_SWRST (DSP_REG_BASE + 0x400 + 0x14)
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#define ADSP_WDT_SWRST_KEY 0x1209
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#define ADSP_WDT_RESTART_RELOAD 0x1971
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#define ADSP_WDT_LENGTH_KEY 0x8
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#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
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/* DSP IPI IRQ */
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#define CPU2DSP_IRQ BIT(0)
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#define DSP2CPU_IRQ BIT(1)
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#define DSP2SPM_IRQ_B BIT(2)
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#endif /* MT_REG_BASE_H */
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‎src/platform/mt8365/include/platform/lib/memory.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Andrew Perepech <andrew.perepech@mediatek.com>
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*/
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#ifdef __SOF_LIB_MEMORY_H__
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#ifndef __PLATFORM_LIB_MEMORY_H__
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#define __PLATFORM_LIB_MEMORY_H__
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#include <rtos/cache.h>
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#include <xtensa/config/core-isa.h>
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#define BOOT_WITH_DRAM /*Use DRAM as SRAM1 for heap related*/
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/* data cache line alignment */
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#define PLATFORM_DCACHE_ALIGN sizeof(void *)
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/*
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* +-----------------------------------+-----------------------------+
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* | | AUDIO_DSP_SHARED_DRAM |
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* +------------+----------------------+---------+---------+---------+
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* | DSP | Sys | Size | 00b | 01b *** | 11b |
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* +------------+------------+---------+---------+---------+---------+
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* | 0x40000000 | 0x1e100000 | 0x8000 | iram0_0 | iram0_0 | iram0_0 |
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* | 0x40008000 | 0x1e108000 | 0x8000 | iram0_1 | iram0_1 | --- |
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* | 0x40010000 | 0x1e110000 | 0x8000 | iram1 | --- | --- |
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* +------------+------------+---------+---------+---------+---------+
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* | 0x1e000000 | 0x1e000000 | 0x40000 | dram0 | dram0 | dram0 |
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* | 0x1e040000 | 0x1e040000 | 0x20000 | dram1 | dram1 | dram1 |
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* | 0x1e060000 | 0x1e060000 | 0x8000 | --- | iram1 | iram1 |
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* | 0x1e068000 | 0x1e068000 | 0x8000 | --- | --- | iram0_1 |
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* +------------+------------+---------+---------+---------+---------+
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*/
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/* BOOT_WITH_DRAM ONLY */
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/* physical DSP addresses */
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#define DRAM_BASE 0x60000000
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#define DRAM_AUDIO_SHARED_SIZE 0x280000
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#define DRAM_SIZE 0x1000000 /*DRAM Size : 16M , need to sync with Host side*/
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#define SRAM_TOTAL_SIZE 0x40000 /*256KB DSP SRAM*/
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#define VECTOR_SIZE 0x628
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#define SRAM0_BASE DRAM_BASE
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#define SRAM0_SIZE (DRAM_SIZE >> 1)
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#define SRAM1_BASE (DRAM_BASE + SRAM0_SIZE)
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#define SRAM1_SIZE \
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(DRAM_SIZE - SRAM0_SIZE - DRAM_AUDIO_SHARED_SIZE - UUID_ENTRY_ELF_SIZE - \
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LOG_ENTRY_ELF_SIZE - EXT_MANIFEST_ELF_SIZE)
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#define DMA_SIZE 0x100000
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#define UUID_ENTRY_ELF_SIZE 0x6000
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#define LOG_ENTRY_ELF_SIZE 0x200000
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#define EXT_MANIFEST_ELF_SIZE 0x100000
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#define UUID_ENTRY_ELF_BASE (SRAM1_BASE + SRAM1_SIZE)
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#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
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#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
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/*
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* The Memory Layout on MT8365 are organised like this :-
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*
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* +--------------------------------------------------------------------------+
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* | Offset | Region | Size |
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* +---------------------+----------------+-----------------------------------+
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* | XCHAL_RESET_VECTOR0 | DSP Vectors | VECTOR_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SRAM0_BASE | fw_ready | SRAM0_SIZE |
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* | | RO Data | |
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* | | module_init | |
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* | | Text | |
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* | | Data | |
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* | | BSS | |
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* +---------------------+----------------+-----------------------------------+
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* | SRAM1_BASE | MAILBOX | SOF_MAILBOX_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_BASE | | |
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* +---------------------+----------------+-----------------------------------+
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*/
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/* Mailbox configuration */
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#define SRAM_OUTBOX_BASE SRAM1_BASE
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#define SRAM_OUTBOX_SIZE 0x1000
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#define SRAM_OUTBOX_OFFSET 0
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#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
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#define SRAM_INBOX_SIZE 0x1000
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#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
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#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
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#define SRAM_DEBUG_SIZE 0x800
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#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
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#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
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#define SRAM_EXCEPT_SIZE 0x800
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#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
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#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
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#define SRAM_STREAM_SIZE 0x1000
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#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
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#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
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#define SRAM_TRACE_SIZE 0x1000
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#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
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/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
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#define SOF_MAILBOX_SIZE \
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(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
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SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
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/* Heap section sizes for module pool */
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#define HEAP_RT_COUNT8 0
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#define HEAP_RT_COUNT16 48
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#define HEAP_RT_COUNT32 48
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#define HEAP_RT_COUNT64 32
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#define HEAP_RT_COUNT128 32
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#define HEAP_RT_COUNT256 32
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#define HEAP_RT_COUNT512 32
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#define HEAP_RT_COUNT1024 4
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#define HEAP_RT_COUNT2048 2
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#define HEAP_RT_COUNT4096 2
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/* Heap section sizes for system runtime heap */
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#define HEAP_SYS_RT_COUNT64 128
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#define HEAP_SYS_RT_COUNT512 16
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#define HEAP_SYS_RT_COUNT1024 8
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/* Heap configuration */
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#define HEAP_SYSTEM_BASE (SRAM1_BASE + SOF_MAILBOX_SIZE)
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#define HEAP_SYSTEM_SIZE 0x6000
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#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE
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#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
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/*24KB*/
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#define HEAP_SYS_RUNTIME_SIZE \
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(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024)
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#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
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/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
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#define HEAP_RUNTIME_SIZE \
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(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
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HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \
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HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
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#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
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#define HEAP_BUFFER_SIZE \
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(SRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE - \
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HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
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#define HEAP_BUFFER_BLOCK_SIZE 0x100
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#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
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#define PLATFORM_HEAP_SYSTEM 1 /* one per core */
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#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */
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#define PLATFORM_HEAP_RUNTIME 1
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#define PLATFORM_HEAP_BUFFER 1
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/* Stack configuration */
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#define SOF_STACK_SIZE 0x8000
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#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/
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#define SOF_STACK_BASE (SRAM1_BASE + SRAM1_SIZE)
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#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
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/* Vector and literal sizes - not in core-isa.h */
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#define SOF_MEM_VECT_LIT_SIZE 0x4
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#define SOF_MEM_VECT_TEXT_SIZE 0x1c
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#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
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#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
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#define SOF_MEM_RESET_LIT_SIZE 0x120
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#define SOF_MEM_VECBASE_LIT_SIZE 0x178
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#define SOF_MEM_RO_SIZE 0x8
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#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE
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/** \brief EDF task's default stack size in bytes. */
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#ifdef CONFIG_COMP_GOOGLE_RTC_AUDIO_PROCESSING
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#define PLATFORM_TASK_DEFAULT_STACK_SIZE (12 * 1024)
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#else
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#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072
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#endif
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#if !defined(__ASSEMBLER__) && !defined(LINKER)
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struct sof;
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/**
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* \brief Data shared between different cores.
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* Does nothing, since mt8195 doesn't support SMP.
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*/
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#define SHARED_DATA
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void platform_init_memmap(struct sof *sof);
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static inline void *platform_shared_get(void *ptr, int bytes)
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{
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return ptr;
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}
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#define uncache_to_cache(address) address
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#define cache_to_uncache(address) address
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#define cache_to_uncache_init(address) address
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#define is_uncached(address) 0
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/**
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* \brief Function for keeping shared data synchronized.
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* It's used after usage of data shared by different cores.
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* Such data is either statically marked with SHARED_DATA
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* or dynamically allocated with SOF_MEM_FLAG_SHARED flag.
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* Does nothing, since mt8195 doesn't support SMP.
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*/
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static inline void *platform_rfree_prepare(void *ptr)
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{
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return ptr;
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}
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#endif
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#define host_to_local(addr) (addr)
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#define local_to_host(addr) (addr)
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#endif /* __PLATFORM_LIB_MEMORY_H__ */
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#else
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#error "This file shouldn't be included from outside of sof/lib/memory.h"
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#endif /* __SOF_LIB_MEMORY_H__ */

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