apl-ssp: setting additional bits in ssp registers

I've added possibility to set some additional bits in ssp registers.
In reference to this there was a need to add quirk field in
sof_ipc_dai_ssp_params struct.

Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>

Author: bkokoszx

src/drivers/apl-ssp.c

@@ -266,6 +266,40 @@ static inline int ssp_set_config(struct dai *dai,
 
 	sscr0 |= SSCR0_MOD | SSCR0_ACS;
 
+	/* Additional hardware settings */
+
+	/* Receiver Time-out Interrupt Disabled/Enabled */
+	sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_TINTE) ?
+		SSCR1_TINTE : 0;
+
+	/* Peripheral Trailing Byte Interrupts Disable/Enable */
+	sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PINTE) ?
+		SSCR1_PINTE : 0;
+
+	/* Transmit data are driven at the same/opposite clock edge specified
+	 * in SSPSP.SCMODE[1:0]
+	 */
+	sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_SMTATF) ?
+		SSCR2_SMTATF : 0;
+
+	/* Receive data are sampled at the same/opposite clock edge specified
+	 * in SSPSP.SCMODE[1:0]
+	 */
+	sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_MMRATF) ?
+		SSCR2_MMRATF : 0;
+
+	/* Enable/disable the fix for PSP slave mode TXD wait for frame
+	 * de-assertion before starting the second channel
+	 */
+	sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD) ?
+		SSCR2_PSPSTWFDFD : 0;
+
+	/* Enable/disable the fix for PSP master mode FSRT with dummy stop &
+	 * frame end padding capability
+	 */
+	sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD) ?
+		SSCR2_PSPSRWFDFD : 0;
+
 	mdivc = 0x1;
 #ifdef CONFIG_CANNONLAKE
 	if (!config->ssp.mclk_rate || config->ssp.mclk_rate > F_24000_kHz) {

src/include/sof/ssp.h

@@ -133,9 +133,13 @@ extern const struct dai_ops ssp_ops;
 #elif defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \
 		|| defined CONFIG_HASWELL || defined CONFIG_BROADWELL
 #define SSCR2_TURM1		BIT(1)
+#define SSCR2_PSPSRWFDFD	BIT(3)
+#define SSCR2_PSPSTWFDFD	BIT(4)
 #define SSCR2_SDFD		BIT(14)
 #define SSCR2_SDPM		BIT(16)
 #define SSCR2_LJDFD		BIT(17)
+#define SSCR2_MMRATF		BIT(18)
+#define SSCR2_SMTATF		BIT(19)
 #endif
 
 

src/include/uapi/ipc.h

@@ -226,6 +226,15 @@ struct sof_ipc_compound_hdr {
 #define SOF_DAI_FMT_INV_MASK		0x0f00
 #define SOF_DAI_FMT_MASTER_MASK		0xf000
 
+#define SOF_DAI_INTEL_SSP_QUIRK_TINTE		(1 << 0) /* ssc1: TINTE */
+#define SOF_DAI_INTEL_SSP_QUIRK_PINTE		(1 << 1) /* ssc1: PINTE */
+#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF		(1 << 2) /* ssc2: SMTATF */
+#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF		(1 << 3) /* ssc2: MMRATF */
+#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD	(1 << 4) /* ssc2: PSPSTWFDFD */
+#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD	(1 << 5) /* ssc2: PSPSRWFDFD*/
+ /* here is the possibility to define others aux macros */
+
+
 /** \brief Types of DAI */
 enum sof_ipc_dai_type {
 	SOF_DAI_INTEL_NONE = 0,	/**< None */
@@ -259,7 +268,7 @@ struct sof_ipc_dai_ssp_params {
 	uint32_t bclk_keep_active;
 	uint32_t fs_keep_active;
 
-	//uint32_t quirks; // FIXME: is 32 bits enough ?
+	uint32_t quirks; // FIXME: is 32 bits enough ?
 
 	/* private data, e.g. for quirks */
 	//uint32_t pdata[10]; // FIXME: would really need ~16 u32