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Set SRAM LDO off on power down - additional power gating on D0->D3 path.
Added assembly macros to control state of LDO for LP and HP SRAM. Macros are used during power down procedure to properly handle LDO state. LDO handling sequence in power down procedure is specific for cAVS 1.5. Signed-off-by: Lech Betlej <lech.betlej@linux.intel.com>
1 parent bc50ce1 commit d5c3828

4 files changed

Lines changed: 161 additions & 10 deletions

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‎src/platform/apollolake/include/platform/Makefile.am‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,4 +12,5 @@ noinst_HEADERS = \
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shim.h \
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timer.h \
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asm_memory_management.h \
15-
power_down.h
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asm_ldo_management.h \
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power_down.h

‎src/platform/apollolake/include/platform/asm_ldo_management.h‎

Lines changed: 131 additions & 0 deletions
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@@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lech Betlej <lech.betlej@linux.intel.com>
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*/
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/**
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* \file platform/apollolake/include/platform/asm_ldo_management.h
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* \brief Macros for controlling LDO state specific for cAVS 1.5
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* \author Lech Betlej <lech.betlej@linux.intel.com>
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*/
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#ifndef ASM_LDO_MANAGEMENT_H
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#define ASM_LDO_MANAGEMENT_H
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#ifndef ASSEMBLY
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#warning "Header can only be used by assembly sources."
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#endif
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#include <platform/shim.h>
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.macro m_cavs_set_ldo_state state, ax
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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s32i \state, \ax, 0
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memw
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// wait loop > 300ns (min 100ns required)
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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.endm
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.macro m_cavs_set_hpldo_state state, ax, ay
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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l32i \ay, \ax, 0
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movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK)
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and \ay, \ax, \ay
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or \state, \ay, \state
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m_cavs_set_ldo_state \state, \ax
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.endm
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.macro m_cavs_set_lpldo_state state, ax, ay
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movi \ax, (SHIM_BASE + SHIM_LDOCTL)
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l32i \ay, \ax, 0
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// LP SRAM mask
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movi \ax, ~(SHIM_LDOCTL_LP_SRAM_MASK)
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and \ay, \ax, \ay
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or \state, \ay, \state
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m_cavs_set_ldo_state \state, \ax
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.endm
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.macro m_cavs_set_ldo_on_state ax, ay, az
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK)
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and \az, \ax, \az
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movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_ON | SHIM_LDOCTL_LP_SRAM_LDO_ON)
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or \ax, \az, \ax
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m_cavs_set_ldo_state \ax, \ay
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.endm
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.macro m_cavs_set_ldo_off_state ax, ay, az
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// wait loop > 300ns (min 100ns required)
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK)
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and \az, \az, \ax
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movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_OFF | SHIM_LDOCTL_LP_SRAM_LDO_OFF)
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or \ax, \ax, \az
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s32i \ax, \ay, 0
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l32i \ax, \ay, 0
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.endm
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.macro m_cavs_set_ldo_bypass_state ax, ay, az
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// wait loop > 300ns (min 100ns required)
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movi \ax, 128
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1 :
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addi \ax, \ax, -1
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nop
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bnez \ax, 1b
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movi \ay, (SHIM_BASE + SHIM_LDOCTL)
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l32i \az, \ay, 0
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movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK)
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and \az, \az, \ax
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movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_BYPASS | SHIM_LDOCTL_LP_SRAM_LDO_BYPASS)
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or \ax, \ax, \az
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s32i \ax, \ay, 0
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l32i \ax, \ay, 0
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.endm
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#endif /* ASM_LDO_MANAGEMENT_H */

‎src/platform/apollolake/include/platform/shim.h‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -145,9 +145,6 @@
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#define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */
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#define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */
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148-
/** \brief LDO Control */
149-
#define SHIM_LDOCTL 0xA4
150-
151148
/** \brief Clock control */
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#define SHIM_CLKCTL 0x78
153150

@@ -219,10 +216,22 @@
219216
/* HP & LP SRAM Power Gating */
220217
#define SHIM_HSPGCTL 0x80
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#define SHIM_LSPGCTL 0x84
222-
#define SHIM_SPSREQ 0xa0
219+
#define SHIM_SPSREQ 0xa0
223220

224221
#define SHIM_SPSREQ_RVNNP (0x1 << 0)
225222

223+
/** \brief LDO Control */
224+
#define SHIM_LDOCTL 0xA4
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226+
#define SHIM_LDOCTL_HP_SRAM_MASK (3 << 0)
227+
#define SHIM_LDOCTL_LP_SRAM_MASK (3 << 2)
228+
#define SHIM_LDOCTL_HP_SRAM_LDO_ON (3 << 0)
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#define SHIM_LDOCTL_LP_SRAM_LDO_ON (3 << 2)
230+
#define SHIM_LDOCTL_HP_SRAM_LDO_BYPASS BIT(0)
231+
#define SHIM_LDOCTL_LP_SRAM_LDO_BYPASS BIT(2)
232+
#define SHIM_LDOCTL_HP_SRAM_LDO_OFF (0 << 0)
233+
#define SHIM_LDOCTL_LP_SRAM_LDO_OFF (0 << 2)
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226235
#define SHIM_HSPGISTS 0xb0
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#define SHIM_LSPGISTS 0xb4
228237

‎src/platform/apollolake/power_down.S‎

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
* \author Lech Betlej <lech.betlej@linux.intel.com>
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*/
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#include <platform/asm_memory_management.h>
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#include <platform/asm_ldo_management.h>
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3839
.section .text, "ax"
3940
.align 64
@@ -86,12 +87,17 @@ power_down:
8687
// if b_enable_lpsram = 0 (bool disable_lpsram) - do not disable lpsram.
8788
beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
8889

89-
9090
_PD_DISABLE_LPSRAM:
91-
m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2
91+
movi temp_reg0, SHIM_LDOCTL_LP_SRAM_LDO_ON
92+
m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2
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94+
m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2
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96+
movi temp_reg0, SHIM_LDOCTL_LP_SRAM_LDO_OFF
97+
m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2
9298

93-
// DISABLE_HPSRAM is aligned so there can be zeros between it
94-
// and last instr.
99+
// DISABLE_HPSRAM is aligned so there can be zeros between
100+
//it and last instr.
95101
j _PD_DISABLE_HPSRAM
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97103
// workaround for incidental gnu assembler bug - no alignment here
@@ -103,10 +109,14 @@ _PD_DISABLE_HPSRAM:
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l32i temp_reg0, pu32_hpsram_mask, 0
104110
beqz temp_reg0, _PD_SLEEP
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106-
// TODO: add full support switching off LDO incl. HW W/A
112+
movi temp_reg0, SHIM_LDOCTL_HP_SRAM_LDO_ON
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m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
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// Disable L2 cache in case it would be enabled
107115

108116
m_cavs_hpsram_power_off temp_reg0, temp_reg1, temp_reg2
109117

118+
movi temp_reg0, SHIM_LDOCTL_HP_SRAM_LDO_OFF
119+
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
110120

111121
// For BXT-P we need to deassert VNN request and select slow XTAL
112122
// as clock source

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