@@ -204,13 +204,18 @@ static void pipeline_trigger_sched_comp(struct pipeline *p,
204204 case COMP_TRIGGER_PAUSE :
205205 case COMP_TRIGGER_STOP :
206206 pipeline_schedule_cancel (p );
207+ p -> status = COMP_STATE_PAUSED ;
207208 break ;
209+ case COMP_TRIGGER_RELEASE :
208210 case COMP_TRIGGER_START :
209211 p -> xrun_bytes = 0 ;
210212
211213 /* playback pipelines need scheduled now, capture pipelines are
212- * scheduled once their initial DMA period is filled by the DAI */
213- if (comp -> params .direction == SOF_IPC_STREAM_PLAYBACK ) {
214+ * scheduled once their initial DMA period is filled by the DAI
215+ * or in resume process
216+ */
217+ if (comp -> params .direction == SOF_IPC_STREAM_PLAYBACK ||
218+ p -> status == COMP_STATE_PAUSED ) {
214219
215220 /* pipelines are either scheduled by timers or DAI/DMA interrupts */
216221 if (p -> ipc_pipe .timer ) {
@@ -221,22 +226,7 @@ static void pipeline_trigger_sched_comp(struct pipeline *p,
221226 pipeline_schedule_copy_idle (p );
222227 }
223228 }
224- break ;
225- case COMP_TRIGGER_RELEASE :
226- p -> xrun_bytes = 0 ;
227-
228- /* in resume process, capture must be
229- * scheduled to to avoid the xrun in DAI component
230- */
231- if (p -> ipc_pipe .timer ) {
232- /* timer - schedule initial copy */
233- pipeline_schedule_copy (p , 0 );
234- } else {
235- /* DAI - schedule initial
236- * pipeline fill when next idle
237- */
238- pipeline_schedule_copy_idle (p );
239- }
229+ p -> status = COMP_STATE_ACTIVE ;
240230 break ;
241231 case COMP_TRIGGER_SUSPEND :
242232 case COMP_TRIGGER_RESUME :
@@ -632,6 +622,7 @@ int pipeline_prepare(struct pipeline *p, struct comp_dev *dev)
632622 component_prepare_buffers_upstream (dev , dev , NULL );
633623 }
634624
625+ p -> status = COMP_STATE_PREPARE ;
635626out :
636627 spin_unlock_irq (& p -> lock , flags );
637628 return ret ;
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