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lgirdwoodlgirdwood
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Merge pull request #95 from singalsu/tplg_add_iir_dmic_pipe
Topology: Add DMIC capture pipeline with gain and high-pass filter
2 parents 7f47792 + 27281d7 commit 6efe3d4

6 files changed

Lines changed: 179 additions & 2 deletions

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‎topology/Makefile.am‎

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@@ -39,7 +39,8 @@ MACHINES = \
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sof-apl-da7219.tplg \
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sof-glk-da7219.tplg \
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sof-icl-nocodec.tplg \
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sof-apl-eq-pcm512x.tplg
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sof-apl-eq-pcm512x.tplg \
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sof-apl-eq-dmic.tplg
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# Uncomment the following line if you want to debug conf files
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.PRECIOUS: %.conf
@@ -79,4 +80,5 @@ EXTRA_DIST = \
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sof-apl-da7219.m4 \
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sof-glk-da7219.m4 \
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sof-icl-nocodec.m4 \
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sof-apl-eq-pcm512x.m4
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sof-apl-eq-pcm512x.m4 \
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sof-apl-eq-dmic.m4

‎topology/m4/eq_fir_coef_flat.m4‎

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# Flat FIR EQ 11-Oct-2018
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CONTROLBYTES_PRIV(EQFIR_priv,
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` bytes "0x18,0x00,0x00,0x00,0x02,0x00,0x01,0x00,'
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` 0x00,0x00,0x00,0x00,0x04,0x00,0xff,0xff,'
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` 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00"'
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)

‎topology/m4/eq_iir_coef_flat.m4‎

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# Flat IIR EQ 11-Oct-2018
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CONTROLBYTES_PRIV(EQIIR_priv,
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` bytes "0x38,0x00,0x00,0x00,0x02,0x00,0x00,0x00,'
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` 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,'
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` 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,0x9e,0x73,0x13,0x20,'
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` 0x00,0x00,0x00,0x00,0xb2,0x7f,0x00,0x00"'
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)

‎topology/m4/eq_iir_coef_highpass_50hz_20db_48khz.m4‎

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# 50 Hz 2nd order high-pass and +20 dB gain 09-Oct-2018
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CONTROLBYTES_PRIV(EQIIR_priv,
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` bytes "0x38,0x00,0x00,0x00,0x02,0x00,0x00,0x00,'
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` 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,'
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` 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,'
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` 0x01,0x00,0x00,0x00,0x63,0xf3,0x96,0xc0,'
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` 0xc6,0x59,0x68,0x7f,0x6d,0x89,0xed,0x1f,'
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` 0x27,0xed,0x24,0xc0,0x6d,0x89,0xed,0x1f,'
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` 0xfc,0xff,0xff,0xff,0xd0,0x4f,0x00,0x00"'
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)

‎topology/sof-apl-eq-dmic.m4‎

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#
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# Topology for Apollo Lake with direct attach digital microphones array
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#
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Apollolake DSP configuration
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include(`platform/intel/bxt.m4')
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include(`platform/intel/dmic.m4')
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#
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# Define the pipelines
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#
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# PCM6 <---- volume <----- DMIC6 (DMIC01)
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#
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dnl PIPELINE_PCM_ADD(pipeline,
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dnl pipe id, pcm, max channels, format,
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dnl frames, deadline, priority, core)
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# Passthrough capture pipeline 13 on PCM 6 using max 4 channels.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-eq-capture.m4,
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1, 6, 4, s32le,
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48, 1000, 0, 0)
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#
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# DAIs configuration
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#
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dnl DAI_ADD(pipeline,
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dnl pipe id, dai type, dai_index, dai_be,
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dnl buffer, periods, format,
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dnl frames, deadline, priority, core)
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# capture DAI is DMIC 0 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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1, DMIC, 0, NoCodec-6,
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PIPELINE_SINK_1, 2, s32le,
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48, 1000, 0, 0)
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dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
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dnl PCM_CAPTURE_ADD(name, pipeline, capture)
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PCM_CAPTURE_ADD(DMIC01, 6, PIPELINE_PCM_1)
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#
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# BE configurations - overrides config in ACPI if present
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#
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dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config)
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DAI_CONFIG(DMIC, 0, 6, NoCodec-6,
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dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max,
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dnl sample_rate,
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dnl fifo word length, type, dai_index, pdm controller config)
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DMIC_CONFIG(1, 500000, 4800000, 40, 60, 48000,
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dnl DMIC_WORD_LENGTH(frame_format)
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DMIC_WORD_LENGTH(s32le), DMIC, 0,
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dnl PDM_CONFIG(type, dai_index, num pdm active, pdm tuples list)
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dnl STEREO_PDM0 is a pre-defined pdm config for stereo capture
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PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1)))
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‎topology/sof/pipe-eq-capture.m4‎

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# Capture Passthrough Pipeline and PCM
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#
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# Pipeline Endpoints for connection are :-
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#
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# host PCM_C <-- B0 <-- sink DAI0
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# Include topology builder
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include(`utils.m4')
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include(`buffer.m4')
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include(`pcm.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`bytecontrol.m4')
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include(`eq_iir.m4')
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#
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# Controls
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#
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# Use 50 Hz highpass response with +20 dB gain
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include(`eq_iir_coef_highpass_50hz_20db_48khz.m4')
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# EQ Bytes control with max value of 255
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C_CONTROLBYTES(EQIIR, PIPELINE_ID,
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CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
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CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
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, , ,
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CONTROLBYTES_MAX(, 316),
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,
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EQIIR_priv)
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#
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# Components and Buffers
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#
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# Host "Highpass Capture" PCM
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# with 0 sink and 2 source periods
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W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2, 2)
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# "EQ 0" has 2 sink period and 2 source periods
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W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "EQIIR"))
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# Capture Buffers
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W_BUFFER(0, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_PASS_MEM_CAP)
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W_BUFFER(1, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_PASS_MEM_CAP)
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#
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# Pipeline Graph
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#
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# host PCM_C <--- B1 <--- EQ_IIR 0 <-- B0 <-- sink DAI0
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P_GRAPH(pipe-pass-capture-PIPELINE_ID, PIPELINE_ID,
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LIST(` ',
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`dapm(Highpass Capture PCM_ID, N_PCMC(PCM_ID))',
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`dapm(N_PCMC(PCM_ID), N_BUFFER(1))',
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`dapm(N_BUFFER(1), N_EQ_IIR(0))',
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`dapm(N_EQ_IIR(0), N_BUFFER(0))'))
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#
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# Pipeline Source and Sinks
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#
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indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(0))
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indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID)
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#
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# PCM Configuration
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#
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PCM_CAPABILITIES(Highpass Capture PCM_ID, COMP_FORMAT_NAME(PIPELINE_FORMAT), 48000, 48000, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)

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