Skip to content
This repository was archived by the owner on Jan 17, 2019. It is now read-only.

Commit baa791f

Browse files
singalsuJaska Uimonen
singalsu
authored and
Jaska Uimonen
committed
Topology: Add Equalizer
This patch adds EQ, bytecontrol, and EQ+volume pipeline m4 macros and an enhanced topology with EQ for UP2 + HiFiberry. There is not yet FIR/IIR type select. The EQ type is currently hardcoded into kernel. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
1 parent 15030d4 commit baa791f

6 files changed

Lines changed: 318 additions & 2 deletions

File tree

‎topology/Makefile.am‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,8 @@ MACHINES = \
3535
sof-apl-wm8804.tplg \
3636
sof-apl-da7219.tplg \
3737
sof-glk-da7219.tplg \
38-
sof-icl-nocodec.tplg
38+
sof-icl-nocodec.tplg \
39+
sof-apl-eq-pcm512x.tplg
3940

4041
# Uncomment the following line if you want to debug conf files
4142
.PRECIOUS: %.conf
@@ -71,4 +72,5 @@ EXTRA_DIST = \
7172
sof-apl-wm8804.m4 \
7273
sof-apl-da7219.m4 \
7374
sof-glk-da7219.m4 \
74-
sof-icl-nocodec.m4
75+
sof-icl-nocodec.m4 \
76+
sof-apl-eq-pcm512x.m4

‎topology/m4/bytecontrol.m4‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
divert(-1)
2+
3+
dnl Define macro for byte control
4+
5+
dnl CONTROLBYTES_MAX(comment, value)
6+
define(`CONTROLBYTES_MAX',
7+
`#$1'
8+
` max STR($2)')
9+
10+
dnl CONTROLMIXER_TLV(comment, value)
11+
define(`CONTROLBYTES_TLV',
12+
`#$1'
13+
` tlv STR($2)')
14+
15+
dnl CONTROLMIXER_OPS(info, comment, get, put)
16+
define(`CONTROLBYTES_OPS',
17+
`ops."ctl" {'
18+
` info STR($1)'
19+
` #$2'
20+
` }')
21+
22+
dnl CONTROLMIXER_OPS(info, comment, get, put)
23+
define(`CONTROLBYTES_EXTOPS',
24+
`extops."extctl" {'
25+
` #$1'
26+
` get STR($2)'
27+
` put STR($3)'
28+
` }')
29+
30+
dnl C_CONTROLMIXER(name, index, ops, base, num_regs, mask, max, tlv)
31+
define(`C_CONTROLBYTES',
32+
`SectionControlBytes.STR($1) {'
33+
`'
34+
` # control belongs to this index group'
35+
` index STR($2)'
36+
`'
37+
` # control uses bespoke driver get/put/info ID for io ops'
38+
` $3'
39+
` # control uses bespoke driver get/put/info ID for ext ops'
40+
` $4'
41+
`'
42+
` base STR($5)'
43+
` num_regs STR($6)'
44+
` mask STR($7)'
45+
` $8'
46+
` $9'
47+
` access ['
48+
` tlv_write'
49+
` tlv_read'
50+
` tlv_callback'
51+
` ]'
52+
`}')
53+
54+
divert(0)dnl

‎topology/m4/eq.m4‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
divert(-1)
2+
3+
dnl Define macro for Eq effect widget
4+
5+
dnl EQ name)
6+
define(`N_EQ', `EQ'PIPELINE_ID`.'$1)
7+
8+
dnl W_EQ(name, format, periods_sink, periods_source, preload, kcontrols_list)
9+
define(`W_EQ',
10+
`SectionVendorTuples."'N_EQ($1)`_tuples_w" {'
11+
` tokens "sof_comp_tokens"'
12+
` tuples."word" {'
13+
` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3)
14+
` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($4)
15+
` SOF_TKN_COMP_PRELOAD_COUNT' STR($5)
16+
` }'
17+
`}'
18+
`SectionData."'N_EQ($1)`_data_w" {'
19+
` tuples "'N_EQ($1)`_tuples_w"'
20+
`}'
21+
`SectionVendorTuples."'N_EQ($1)`_tuples_str" {'
22+
` tokens "sof_comp_tokens"'
23+
` tuples."string" {'
24+
` SOF_TKN_COMP_FORMAT' STR($2)
25+
` }'
26+
`}'
27+
`SectionData."'N_EQ($1)`_data_str" {'
28+
` tuples "'N_EQ($1)`_tuples_str"'
29+
`}'
30+
`SectionWidget."'N_EQ($1)`" {'
31+
` index "'PIPELINE_ID`"'
32+
` type "effect"'
33+
` no_pm "true"'
34+
` data ['
35+
` "'N_EQ($1)`_data_w"'
36+
` "'N_EQ($1)`_data_str"'
37+
` ]'
38+
` bytes ['
39+
$6
40+
` ]'
41+
`}')
42+
43+
divert(0)dnl

‎topology/sof-apl-eq-pcm512x.m4‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
#
2+
# Topology for generic Apollolake UP^2 with pcm512x codec.
3+
#
4+
5+
# Include topology builder
6+
include(`utils.m4')
7+
include(`dai.m4')
8+
include(`pipeline.m4')
9+
include(`ssp.m4')
10+
11+
# Include TLV library
12+
include(`common/tlv.m4')
13+
14+
# Include Token library
15+
include(`sof/tokens.m4')
16+
17+
# Include Apollolake DSP configuration
18+
include(`platform/intel/bxt.m4')
19+
20+
#
21+
# Define the pipelines
22+
#
23+
# PCM0 ----> volume -----> SSP5 (pcm512x)
24+
#
25+
26+
# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
27+
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
28+
PIPELINE_PCM_ADD(sof/pipe-eq-volume-playback.m4,
29+
1, 0, 2, s32le,
30+
48, 1000, 0, 0)
31+
32+
#
33+
# DAIs configuration
34+
#
35+
36+
# playback DAI is SSP5 using 2 periods
37+
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
38+
DAI_ADD(sof/pipe-dai-playback.m4,
39+
1, SSP, 5, SSP5-Codec,
40+
PIPELINE_SOURCE_1, 2, s24le,
41+
48, 1000, 0, 0)
42+
43+
# PCM Low Latency, id 0
44+
PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1)
45+
46+
#
47+
# BE configurations - overrides config in ACPI if present
48+
#
49+
50+
DAI_CONFIG(SSP, 5, 0, SSP5-Codec,
51+
SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
52+
SSP_CLOCK(bclk, 3072000, codec_slave),
53+
SSP_CLOCK(fsync, 48000, codec_slave),
54+
SSP_TDM(2, 32, 3, 3),
55+
SSP_CONFIG_DATA(SSP, 5, 24)))

‎topology/sof/pipe-eq-volume-playback.m4‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
# Low Latency Passthrough with volume Pipeline and PCM
2+
#
3+
# Pipeline Endpoints for connection are :-
4+
#
5+
# host PCM_P --> B0 --> EQ 0 --> B1 --> Volume 0 --> B2 --> sink DAI0
6+
7+
# Include topology builder
8+
include(`utils.m4')
9+
include(`buffer.m4')
10+
include(`pcm.m4')
11+
include(`pga.m4')
12+
include(`dai.m4')
13+
include(`mixercontrol.m4')
14+
include(`bytecontrol.m4')
15+
include(`pipeline.m4')
16+
include(`eq.m4')
17+
18+
#
19+
# Controls
20+
#
21+
# Volume Mixer control with max value of 32
22+
C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID,
23+
CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256),
24+
CONTROLMIXER_MAX(, 32),
25+
false,
26+
CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3),
27+
Channel register and shift for Front Left/Right,
28+
LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
29+
30+
# EQ Bytes control with max value of 255
31+
C_CONTROLBYTES(EQ, PIPELINE_ID,
32+
CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
33+
CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
34+
, , ,
35+
CONTROLBYTES_MAX(, 10))
36+
37+
#
38+
# Components and Buffers
39+
#
40+
41+
# Host "Passthrough Playback" PCM
42+
# with 2 sink and 0 source periods
43+
W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, 2, 0, 2)
44+
45+
# "Volume" has 2 source and 2 sink periods
46+
W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "Master Playback Volume PIPELINE_ID"))
47+
48+
# "EQ 0" has 2 sink period and 2 source periods
49+
W_EQ(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "EQ"))
50+
51+
# Playback Buffers
52+
W_BUFFER(0, COMP_BUFFER_SIZE(2,
53+
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
54+
PLATFORM_HOST_MEM_CAP)
55+
W_BUFFER(1, COMP_BUFFER_SIZE(2,
56+
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
57+
PLATFORM_HOST_MEM_CAP)
58+
W_BUFFER(2, COMP_BUFFER_SIZE(2,
59+
COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
60+
PLATFORM_DAI_MEM_CAP)
61+
62+
#
63+
# Pipeline Graph
64+
#
65+
# host PCM_P --> B0 --> EQ 0 --> B1 --> Volume 0 --> B2 --> sink DAI0
66+
67+
P_GRAPH(pipe-pass-vol-playback-PIPELINE_ID, PIPELINE_ID,
68+
LIST(` ',
69+
`dapm(N_PCMP(PCM_ID), Passthrough Playback PCM_ID)',
70+
`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
71+
`dapm(N_EQ(0), N_BUFFER(0))',
72+
`dapm(N_BUFFER(1), N_EQ(0))',
73+
`dapm(N_PGA(0), N_BUFFER(1))',
74+
`dapm(N_BUFFER(2), N_PGA(0))'))
75+
76+
#
77+
# Pipeline Source and Sinks
78+
#
79+
indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
80+
indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_ID)
81+
82+
83+
#
84+
# PCM Configuration
85+
86+
#
87+
PCM_CAPABILITIES(Passthrough Playback PCM_ID, `S32_LE,S24_LE,S16_LE', 48000, 48000, 2, 8, 2, 16, 192, 16384, 65536, 65536)
88+

‎topology/test/test-equalizer-playback-ssp.m4‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
#
2+
# Topology for pass through pipeline
3+
#
4+
5+
# Include topology builder
6+
include(`pipeline.m4')
7+
include(`dai.m4')
8+
include(`utils.m4')
9+
10+
# Include TLV library
11+
include(`common/tlv.m4')
12+
13+
# Include Token library
14+
include(`sof/tokens.m4')
15+
16+
# Include Baytrail DSP configuration
17+
include(`dsps/byt.m4')
18+
19+
#
20+
# Machine Specific Config - !! MUST BE SET TO MATCH TEST MACHINE DRIVER !!
21+
#
22+
# TEST_PIPE_NAME - Pipe name
23+
# TEST_DAI_LINK_NAME - BE DAI link name e.g. "NoCodec"
24+
# TEST_SSP_PORT - SSP port number e.g. 2
25+
# TEST_SSP_FORMAT - SSP data format e.g s16le
26+
# TEST_PIPE_FORMAT - Pipeline format e.g. s16le
27+
# TEST_SSP_MCLK - SSP MCLK in Hz
28+
# TEST_SSP_BCLK - SSP BCLK in Hz
29+
# TEST_SSP_PHY_BITS - SSP physical slot size
30+
# TEST_SSP_DATA_BITS - SSP data slot size
31+
#
32+
33+
#
34+
# Define the pipeline
35+
#
36+
# PCM0 <---> SSP TEST_SSP_PORT
37+
#
38+
39+
# Passthrough playback pipeline 1 on PCM 0 using max 2 channels of s24le.
40+
# Schedule 48 frames per 1000us deadline on core 0 with priority 0
41+
# Use DMAC 0 channel 1 for PCM audio playback data
42+
43+
PIPELINE_PCM_DAI_ADD(sof/pipe-TEST_PIPE_NAME-playback.m4,
44+
1, 0, 2, TEST_PIPE_FORMAT,
45+
48, 1000, 0, 0, 0, 1,
46+
SSP, TEST_SSP_PORT, TEST_SSP_FORMAT, 2)
47+
#
48+
# DAI configuration
49+
#
50+
# SSP port TEST_SSP_PORT is our only pipeline DAI
51+
#
52+
53+
# playback DAI is SSP TEST_SSP_PORT using 2 periods
54+
# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
55+
DAI_ADD(sof/pipe-dai-playback.m4,
56+
1, SSP, TEST_SSP_PORT, TEST_DAI_LINK_NAME,
57+
PIPELINE_SOURCE_1, 2, TEST_SSP_FORMAT,
58+
48, 1000, 0, 0)
59+
60+
# PCM Passthrough
61+
PCM_PLAYBACK_ADD(Passthrough, 3, 0, 0, PIPELINE_PCM_1)
62+
63+
#
64+
# BE configurations - overrides config in ACPI if present
65+
#
66+
# Clocks masters wrt codec
67+
#
68+
# TEST_SSP_DATA_BITS bit I2S using TEST_SSP_PHY_BITS bit sample conatiner on SSP TEST_SSP_PORT
69+
#
70+
DAI_CONFIG(SSP, TEST_SSP_PORT, TEST_DAI_LINK_NAME, I2S, TEST_SSP_DATA_BITS,
71+
DAI_CLOCK(mclk, TEST_SSP_MCLK, slave),
72+
DAI_CLOCK(bclk, TEST_SSP_BCLK, slave),
73+
DAI_CLOCK(fsync, 48000, slave),
74+
DAI_TDM(2, TEST_SSP_PHY_BITS, 3, 3))

0 commit comments

Comments
 (0)