[fix-arm-support] gg_tt.mad: undefine__ARM_NEON for cppnone on arm/apple (with DanieleM)

Results on an Apple M1 (thanks Olivier!)

for avx in none sse4; do ./build.${avx}_m_inl0_hrd0/check_cpp.exe -p 1024 256 1
  | \egrep '(EvtsPerSec\[MECalcOnly\]|MeanMatrixElemValue|fptype_sv)'; done

Internal loops fptype_sv    = SCALAR ('none': ~vector[1], no SIMD)
EvtsPerSec[MECalcOnly] (3a) = ( 5.535410e+05                 )  sec^-1
MeanMatrixElemValue         = ( 2.080788e+00 +- 6.803789e-03 )  GeV^0

Internal loops fptype_sv    = VECTOR[2] ('sse4': ARM NEON, 128bit) [cxtype_ref=NO]
EvtsPerSec[MECalcOnly] (3a) = ( 8.327442e+05                 )  sec^-1
MeanMatrixElemValue         = ( 2.080788e+00 +- 6.803789e-03 )  GeV^0

Author: valassi

epochX/cudacpp/gg_tt.mad/SubProcesses/cudacpp.mk

@@ -527,17 +527,19 @@ ifeq ($(UNAME_P),ppc64le)
   else ifeq ($(BACKEND),cpp512z)
     $(error Invalid SIMD BACKEND='$(BACKEND)': only 'cppnone' and 'cppsse4' are supported on PowerPC for the moment)
   endif
-else ifeq ($(UNAME_P),arm)
-  ifeq ($(BACKEND),cppsse4)
-    override AVXFLAGS = -D__ARM_NEON__ # ARM NEON with 128 width (Q/quadword registers)
+else ifeq ($(UNAME_P),arm) # ARM on Apple silicon
+  ifeq ($(BACKEND),cppnone) # this internally undefines __ARM_NEON
+    override AVXFLAGS = -DMGONGPU_NOARMNEON
+  else ifeq ($(BACKEND),cppsse4) # __ARM_NEON is always defined on Apple silicon
+    override AVXFLAGS =
   else ifeq ($(BACKEND),cppavx2)
     $(error Invalid SIMD BACKEND='$(BACKEND)': only 'cppnone' and 'cppsse4' are supported on ARM for the moment)
   else ifeq ($(BACKEND),cpp512y)
     $(error Invalid SIMD BACKEND='$(BACKEND)': only 'cppnone' and 'cppsse4' are supported on ARM for the moment)
   else ifeq ($(BACKEND),cpp512z)
     $(error Invalid SIMD BACKEND='$(BACKEND)': only 'cppnone' and 'cppsse4' are supported on ARM for the moment)
   endif
-else ifeq ($(UNAME_P),aarch64)
+else ifeq ($(UNAME_P),aarch64) # ARM on Linux
   ifeq ($(BACKEND),cppnone) # +nosimd ensures __ARM_NEON is absent
     override AVXFLAGS = -march=armv8-a+nosimd
   else ifeq ($(BACKEND),cppsse4) # +simd ensures __ARM_NEON is present (128 width Q/quadword registers)

epochX/cudacpp/gg_tt.mad/src/mgOnGpuConfig.h

@@ -214,6 +214,11 @@ namespace mgOnGpu
 using mgOnGpu::fptype;
 using mgOnGpu::fptype2;
 
+// Undefine ARM_NEON (hack for cppnone on Apple silicon ARM)
+#ifdef MGONGPU_NOARMNEON
+#undef __ARM_NEON
+#endif
+
 // C++ SIMD vectorization width (this will be used to set neppV)
 #ifdef MGONGPUCPP_GPUIMPL // CUDA and HIP implementations have no SIMD
 #undef MGONGPU_CPPSIMD