From 099b5a77e4cd82a226ba77dca392e13f048cc636 Mon Sep 17 00:00:00 2001 From: Marco Barbone Date: Mon, 6 Jul 2026 16:09:05 -0400 Subject: [PATCH] Add an explicit SSE2 path for batch_bool_constant masks where the three low lanes are active and lane 3 is zero ({T,T,T,F} = countr_one()==3). load_masked: movsd (lanes 0,1) + movss (lane 2) + shufps into [lo0, lo1, ss0, 0]. store_masked: storel_pi (lanes 0,1) + movehl+store_ss (lane 2). Without this both paths fell through to the common-arch scalar-buffer fallback (zero-init std::array + element-wise scatter + aligned reload), --- include/xsimd/arch/xsimd_sse2.hpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/xsimd/arch/xsimd_sse2.hpp b/include/xsimd/arch/xsimd_sse2.hpp index 0a95aae8b..5748ed831 100644 --- a/include/xsimd/arch/xsimd_sse2.hpp +++ b/include/xsimd/arch/xsimd_sse2.hpp @@ -1147,6 +1147,11 @@ namespace xsimd { return _mm_loadh_pi(_mm_setzero_ps(), reinterpret_cast<__m64 const*>(mem + 2)); } + else XSIMD_IF_CONSTEXPR(mask.countr_one() == 3) + { + __m128 const lo2 = _mm_castsi128_ps(_mm_loadl_epi64(reinterpret_cast<__m128i const*>(mem))); + return _mm_shuffle_ps(lo2, _mm_load_ss(mem + 2), _MM_SHUFFLE(3, 0, 1, 0)); + } else { return load_masked(mem, mask, convert {}, Mode {}, common {}); @@ -1185,6 +1190,11 @@ namespace xsimd { _mm_storeh_pi(reinterpret_cast<__m64*>(mem + 2), src); } + else XSIMD_IF_CONSTEXPR(mask.countr_one() == 3) + { + _mm_storel_pi(reinterpret_cast<__m64*>(mem), src); + _mm_store_ss(mem + 2, _mm_movehl_ps(src, src)); + } else { store_masked(mem, src, mask, Mode {}, common {});