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add codesys hde2e demo: Dockerfile, PLC data bundles, configs, hde2e orchestrator, and sudo/mount fixes
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.gitignore

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# OS-X files
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.DS_Store
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# Docker image tarballs
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*.tar
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###############################################################################
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# Copyright CODESYS Development GmbH
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###############################################################################
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# The referenced base image in this file can be downloaded from the Homepage of OSADL. The base image is a binary-only image for delayed source code delivery.
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# https://www.osadl.org/OSADL-Container-Base-Image.osadl-container-base-image.0.html?&no_cache=1&sword_list%5B0%5D=docker
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# Add it to your own registry and replace the FROM statement with your URL.
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# Alteratively you can directly pull the base image for immediate source code delivery with all sources directly from docker-hub.
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# To do that replace the FROM statement with:
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FROM osadl/debian-docker-base-image:bookworm-amd64-latest
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#FROM repoman.codesys.com:50000/config/standard/osadl-bin/debian/amd64/bookworm:develop
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ENV CONTAINER=true
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USER root
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ENV USER=root
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EXPOSE 443
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EXPOSE 4840
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EXPOSE 8080
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EXPOSE 11740
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RUN apt-get update && apt-get install -y procps libcap2-bin libpciaccess0 \
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intel-cmt-cat python3 python3-pip python3-yaml \
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&& apt-get source --download-only libcap2 procps libpciaccess 2>/dev/null \
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&& rm -rf /var/lib/apt/lists/*
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ARG CODESYSCONTROL_DEB=codesyscontrol_virtuallinux_4.18.0.0*_amd64.deb
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ADD ${CODESYSCONTROL_DEB} /tmp/
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ADD Docker_copyright_* /
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RUN cd /tmp; cd /tmp; dpkg -i ${CODESYSCONTROL_DEB}; rm ${CODESYSCONTROL_DEB};
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WORKDIR /var/opt/codesys/
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ENTRYPOINT [ "/opt/codesys/scripts/startup.sh" ]
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CMD []
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;virtuallinux
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[CmpLog]
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Logger.0.Filter=0x0000000F
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[ComponentManager]
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Component.1=CmpBACnet
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Component.2=CmpBACnet2
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Component.3=CmpPLCHandler
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Component.4=CmpGwClient
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Component.5=CmpXMLParser
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Component.6=CmpGwClientCommDrvTcp
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Component.7=CmpRetain
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;Component.8=CmpGwClientCommDrvShm ; enable only if necessary, can result in higher cpu load
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;Component.9=SysPci ; enable when using Hilscher CIFX
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;Component.10=CmpHilscherCIFX ; enable when using Hilscher CIFX
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[CmpApp]
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Bootproject.RetainMismatch.Init=1
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;RetainType.Applications=InSRAM
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Application.1=Control
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[CmpRedundancyConnectionIP]
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[CmpRedundancy]
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[CmpSrv]
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[IoDrvEtherCAT]
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{
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"plcName": "Control_PLC_01",
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"controller": [
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{
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"name": "Controller_01",
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"pub": [
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{
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"ip": "192.168.10.15",
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"pubId": 11,
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"wrGroupId": 13,
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"dataSetId": 110,
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"task": {
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"Name": "PubSubTask",
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"Interval": 500,
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"Priority": 1
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}
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}
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],
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"sub": [
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{
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"ip": "192.168.10.15",
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"pubId": 12,
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"wrGroupId": 14,
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"dataSetId": 100,
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"task": null
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}
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],
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"processing": {
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"iterations": 10,
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"task": {
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"Name": "ProcessingTask",
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"Interval": 5000,
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"Priority": 2
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}
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},
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"logging": {
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"enabled": true,
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"task": {
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"Name": "FileLoggingTask",
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"Interval": 50000,
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"Priority": 5
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}
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}
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}
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]
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}
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{
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"plcName": "Control_PLC_02",
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"controller": [
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{
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"name": "Controller_02",
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"pub": [
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{
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"ip": "192.168.10.16",
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"pubId": 21,
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"wrGroupId": 23,
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"dataSetId": 110,
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"task": {
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"Name": "PubSubTask",
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"Interval": 500,
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"Priority": 1
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}
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}
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],
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"sub": [
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{
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"ip": "192.168.10.16",
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"pubId": 22,
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"wrGroupId": 24,
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"dataSetId": 100,
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"task": null
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}
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],
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"processing": {
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"iterations": 10,
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"task": {
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"Name": "ProcessingTask",
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"Interval": 5000,
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"Priority": 2
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}
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},
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"logging": {
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"enabled": true,
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"task": {
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"Name": "FileLoggingTask",
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"Interval": 50000,
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"Priority": 5
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}
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}
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}
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]
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}
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;virtuallinux
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[CmpLog]
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Logger.0.Filter=0x0000000F
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[ComponentManager]
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Component.1=CmpBACnet
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Component.2=CmpBACnet2
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Component.3=CmpPLCHandler
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Component.4=CmpGwClient
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Component.5=CmpXMLParser
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Component.6=CmpGwClientCommDrvTcp
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Component.7=CmpRetain
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;Component.8=CmpGwClientCommDrvShm ; enable only if necessary, can result in higher cpu load
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;Component.9=SysPci ; enable when using Hilscher CIFX
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;Component.10=CmpHilscherCIFX ; enable when using Hilscher CIFX
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[CmpApp]
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Bootproject.RetainMismatch.Init=1
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;RetainType.Applications=InSRAM
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Application.1=IO
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[CmpRedundancyConnectionIP]
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[CmpRedundancy]
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[CmpSrv]
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[IoDrvEtherCAT]
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{
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"plcName": "IO_PLC_01",
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"io": [
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{
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"name": "IO_01",
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"pub": [
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{
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"ip": "192.168.10.12",
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"pubId": 12,
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"wrGroupId": 14,
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"dataSetId": 100,
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"task": {
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"Name": "PubSubTask",
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"Interval": 500,
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"Priority": 1
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}
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}
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],
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"sub": [
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{
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"ip": "192.168.10.12",
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"pubId": 11,
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"wrGroupId": 13,
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"dataSetId": 110,
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"task": null
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}
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],
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"benchmarking": {
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"task": {
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"Name": "BenchmarkingTask",
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"Interval": 500,
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"Priority": 2
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}
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},
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"logging": {
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"enabled": true,
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"task": {
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"Name": "FileLoggingTask",
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"Interval": 50000,
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"Priority": 5
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}
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}
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}
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]
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}
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{
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"plcName": "IO_PLC_02",
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"io": [
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{
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"name": "IO_02",
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"pub": [
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{
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"ip": "192.168.10.13",
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"pubId": 22,
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"wrGroupId": 24,
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"dataSetId": 100,
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"task": {
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"Name": "PubSubTask",
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"Interval": 500,
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"Priority": 1
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}
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}
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],
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"sub": [
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{
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"ip": "192.168.10.13",
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"pubId": 21,
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"wrGroupId": 23,
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"dataSetId": 110,
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"task": null
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}
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],
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"benchmarking": {
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"task": {
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"Name": "BenchmarkingTask",
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"Interval": 500,
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"Priority": 2
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}
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},
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"logging": {
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"enabled": true,
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"task": {
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"Name": "FileLoggingTask",
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"Interval": 50000,
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"Priority": 5
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}
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}
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}
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]
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}
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# RDT/CAT Configuration for Control PLCs
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# Based on Intel Cache Allocation Technology (CAT) / Resource Director Technology (RDT)
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# Global RDT Settings
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rdt:
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enabled: true
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interface: "os" # Use OS interface (resctrl) - required for PID assignment
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reset_before_apply: true # Reset RDT configuration before applying new settings
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# Class of Service (COS) Definitions
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# Class 0 is default, Classes 1-15 can be configured (hardware dependent)
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classes:
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# Class 1: Real-time Control PLC cores with dedicated L3 cache
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- id: 1
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name: "RT_Control_Cores"
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description: "Real-time cores for Control PLC with dedicated cache allocation"
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# L3 cache mask (hex): 0x0f = lower 4 ways of L3 cache (bits 0-3)
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# Adjust based on your processor's cache configuration
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l3_mask: "0x0f"
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# L2 cache mask (optional, if supported by hardware)
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# l2_mask: "0xf"
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# Memory Bandwidth Allocation (percentage, optional)
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mba: 100
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# CPU cores assigned to this class
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cores: [3, 5, 7, 9]
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# PIDs will be assigned dynamically based on container
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pids: []
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# Class 2: Non-real-time cores with shared cache
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- id: 2
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name: "Non_RT_Cores"
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description: "Non-real-time cores with shared cache"
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# L3 cache mask: 0xf0 = upper 4 ways of L3 cache (bits 4-7)
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l3_mask: "0xf0"
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mba: 50
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cores: [0, 1, 2, 4, 6, 8]
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pids: []
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# IRQ Affinity Configuration
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irq_affinity:
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enabled: true
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# Cores for handling interrupts (non-RT cores to avoid RT interference)
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irq_cores: "0,1,2"
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# Move RCU tasks to non-RT cores
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rcu_cores: "0,1,2"
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# Core Isolation Settings
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core_isolation:
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# RT cores that should be isolated
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isolated_cores: [3, 5, 7, 9]
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# Kernel parameters that should be set (add to kernel cmdline):
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# isolcpus=3,5,7,9
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# nohz_full=3,5,7,9
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# rcu_nocbs=3,5,7,9
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# irqaffinity=0,1,2
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# Instance-specific settings for Control PLCs
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instances:
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Control_PLC_01:
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class_id: 1
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cpu_affinity: "3,5" # Specific cores for this instance
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priority: 95 # RT priority (1-99, higher = more priority)
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enable_rdtset: true # Use rdtset wrapper when starting CODESYS
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Control_PLC_02:
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class_id: 1
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cpu_affinity: "7,9" # Different cores for second instance
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priority: 95
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enable_rdtset: true
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# Monitoring Configuration
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monitoring:
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enabled: false
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interval: 1 # seconds
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metrics:
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- llc_occupancy # Last Level Cache occupancy
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- mbm_local # Memory Bandwidth Monitoring - local
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- mbm_total # Memory Bandwidth Monitoring - total

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