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85c268f
feat(aten): automatic HF model → PLENA ISA compiler
booth-algo Apr 27, 2026
6df4a4c
rename: model_compiler.py → plena_parser.py
booth-algo Apr 27, 2026
1f65319
rename: plena_parser.py → plena_frontend.py
booth-algo Apr 27, 2026
81061b5
feat(plena_frontend): native-dimension compilation with multi-head at…
booth-algo Apr 28, 2026
a5be39a
fix: audit fixes — assertions, docstring, VRAM padding
booth-algo Apr 28, 2026
0700e80
feat(plena_frontend): on-chip K/V projections + RoPE
booth-algo Apr 28, 2026
e94db75
feat(plena_frontend): true e2e — real embeddings + lm_head + multi-layer
booth-algo Apr 28, 2026
0d9b180
feat(plena_frontend): three-way comparison — HF float32 vs golden vs …
booth-algo Apr 28, 2026
a6beac2
feat: causal masking + real embeddings + lm_head + three-way comparison
booth-algo Apr 28, 2026
7ece0a7
feat: add layer progress markers to ISA output for tracking
booth-algo Apr 29, 2026
7881fb1
fix: add load_toml_config to compiler/utils/load_config.py
booth-algo May 1, 2026
2021b5d
feat: golden_precision ablation for quantization gap proof
booth-algo May 1, 2026
eb5a8b6
fix(golden): BF16 truncation at all pipeline stages + K-split temp fix
booth-algo May 7, 2026
0cbf9ba
fix(golden): use MXFP8-quantized X as golden input, matching HBM
booth-algo May 8, 2026
18f819a
feat: VRAM-in-the-loop stage comparison for emulator validation
booth-algo May 8, 2026
17f50d8
fix(ci): guard toml import for CI environments without toml package
booth-algo May 9, 2026
f5b9e22
style: clean up informal comments in vram_stage_compare
booth-algo May 9, 2026
8501754
fix: use 'compiler' not 'PLENA_Compiler' for doc paths (post-merge fix)
booth-algo May 10, 2026
6ad4228
fix: revert to PLENA_Compiler path (matches production layout)
booth-algo May 10, 2026
c6a61d4
refactor: split PLENA compiler DSL and ISA layers
booth-algo May 11, 2026
5d0447d
refactor: slim ATen compiler path
booth-algo May 12, 2026
5e4bed6
refactor: split ATen frontend references
booth-algo May 12, 2026
f989e1c
refactor: call PLENA compiler directly from ATen frontend
booth-algo May 12, 2026
a0ae671
refactor: route HF frontend through aten ops
booth-algo May 12, 2026
50cd8b4
refactor: split memory state from matrix ISA
booth-algo May 12, 2026
ad2983e
refactor: remove tile compiler compatibility alias
booth-algo May 12, 2026
01c0a32
refactor: remove plena compiler compatibility facade
booth-algo May 12, 2026
274a1b0
docs: add aten package tree
booth-algo May 12, 2026
f110f05
refactor: remove remaining compatibility shims
booth-algo May 12, 2026
a344f1d
docs: refresh generator path comment
booth-algo May 12, 2026
a74454d
docs: refresh sim env path comments
booth-algo May 12, 2026
2af064f
refactor: move ATen e2e runner out of generator
booth-algo May 12, 2026
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2 changes: 1 addition & 1 deletion asm_templates/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
from .elementwise_add_asm import elementwise_add_asm
from .embedding_asm import embedding_asm
from .ffn_asm import ffn_asm, ffn_intermediate_asm, ffn_up_silu_asm
from .flash_attn_asm import flash_attn_asm
from .flashattn import flash_attn_asm
from .gelu_asm import gelu_asm
from .im2col_asm import im2col_asm
from .im2col_asm_no_shift import im2col_asm_no_shift
Expand Down
50 changes: 0 additions & 50 deletions asm_templates/flash_attn_asm.py

This file was deleted.

Empty file.
Empty file removed asm_templates/load_int.py
Empty file.
10 changes: 5 additions & 5 deletions asm_templates/tests/test_vram_sub_projection.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
Verifies the extracted free function produces the expected ISA output for
looped/unrolled and transposed/non-transposed variants, and asserts
byte-identical parity with the delegating
``TileCompiler._vram_sub_projection_asm_impl`` method.
``IsaCompiler._vram_sub_projection_asm_impl`` method.
"""

import sys
Expand Down Expand Up @@ -95,10 +95,10 @@ def test_unrolled_no_loops(self):
self.assertIn("M_MM_WO", asm)

def test_output_byte_identical_to_method(self):
"""The free function must produce byte-identical output to TileCompiler's method."""
from compiler.aten.plena_compiler import TileCompiler
"""The free function must produce byte-identical output to IsaCompiler's method."""
from compiler.aten.plena import IsaCompiler

tc = TileCompiler(mlen=64, blen=4, unroll_loops=False)
compiler = IsaCompiler(mlen=64, blen=4, unroll_loops=False)

method_kwargs = dict(
header_lines=["; header"],
Expand All @@ -113,7 +113,7 @@ def test_output_byte_identical_to_method(self):
caller_name="test",
)

method_out = tc._vram_sub_projection_asm_impl(**method_kwargs)
method_out = compiler._vram_sub_projection_asm_impl(**method_kwargs)
free_out = vram_sub_projection_asm_impl(
mlen=64,
blen=4,
Expand Down
4 changes: 2 additions & 2 deletions asm_templates/vram_sub_projection_asm.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
"""Pure emitter for VRAM sub-projection ISA.

Shared implementation kernel used by ``TileCompiler.vram_sub_projection_asm``
and ``TileCompiler.vram_sub_projection_T_asm``. The caller resolves all
Shared implementation kernel used by ``IsaCompiler.vram_sub_projection_asm``
and ``IsaCompiler.vram_sub_projection_T_asm``. The caller resolves all
instance-dependent state (register allocator, tile layouts, MRAM addresses,
``unroll_loops`` default) and passes it in as plain parameters, so this
emitter can be unit-tested in isolation.
Expand Down
38 changes: 15 additions & 23 deletions aten/__init__.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
"""compiler.aten — ATen-style PLENA compiler path.

PlenaCompiler DSL + op backend registry. Pairs with compiler.generator
PlenaCompiler program builder + op backend registry. Pairs with compiler.generator
for the two-path compiler (template vs. aten).
"""

Expand All @@ -9,30 +9,22 @@
PLENA_PKG_DIR = Path(__file__).parent
NATIVE_OPS_YAML = PLENA_PKG_DIR / "native_ops.yaml"

from compiler.aten.plena_compiler import ( # noqa: E402, F401
from compiler.aten.isa_builder import ( # noqa: E402, F401
Comment,
Instr,
IsaBuilder,
Register,
addr,
fp,
gp,
)
from compiler.aten.plena import ( # noqa: E402, F401
FPVar,
InputVar,
IsaCompiler,
MemoryStateMixin,
PlenaCompiler,
TileCompiler,
DeveloperCompiler,
RegisterAllocator,
TensorVar,
InputVar,
VRAMMatrixVar,
FPVar,
TensorKind,
tensor_kind,
Tensor,
TensorInfo,
TileLayout,
MemoryBlock,
VirtualMemoryManager,
MRAMAllocator,
VRAMAllocator,
FPRAMAllocator,
SubMatrixInfo,
MatrixBlockLayout,
VRAMSubMatrixInfo,
VRAMMatrixBlockLayout,
MemoryObjectInfo,
FPRAMObjectLayout,
)
from compiler.aten.ops.registry import OpRegistry, Backend # noqa: E402, F401
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