Add RTL-config CLM60 simulator harness

[booth-algo]

Summary

• add a CLM60 sliced decoder harness that temporarily derives simulator settings from local PLENA_RTL configuration.svh and precision.svh
• teach the emulator/config/testbench path to handle RTL e6m5 scalar/vector storage and sub-byte MX HBM packing
• make golden/result decoding use active TOML precision instead of hard-coded BF16/MXFP8 assumptions

Verification

• uv run ruff check transactional_emulator/testbench/models/clm60m_rtl_config_test.py transactional_emulator/testbench/rtl_config.py transactional_emulator/testbench/sim_env_utils.py transactional_emulator/testbench/emulator_runner.py transactional_emulator/testbench/sliced_layer_test_builder.py transactional_emulator/tools/check_mem.py transactional_emulator/tools/create_sim_env.py tools/memory_mapping/memory_map.py
• uv run python -m py_compile transactional_emulator/testbench/models/clm60m_rtl_config_test.py transactional_emulator/testbench/rtl_config.py transactional_emulator/testbench/sim_env_utils.py transactional_emulator/testbench/emulator_runner.py transactional_emulator/testbench/sliced_layer_test_builder.py transactional_emulator/tools/check_mem.py transactional_emulator/tools/create_sim_env.py tools/memory_mapping/memory_map.py
• nix develop --command cargo check
• nix develop --command uv run python transactional_emulator/testbench/models/clm60m_rtl_config_test.py --rtl-root /home/khl22/new_plena/PLENA_RTL

Notes

• The CLM60 RTL-config harness completes without crashing and exercises MLEN=16/VLEN=16/BLEN=8 plus e6m5/e1m2/e4m3 precision from the local RTL headers.
• Current numeric comparison still needs follow-up: simulator output at the compared result rows is all zeros while the active-precision golden is ~1e-6 to 1e-5. The existing allclose gate passes only because atol=0.2, so this PR exposes the remaining correctness issue rather than proving numerical agreement.