Skip to content

Add intrinsics for the new FP conversions introduced by the 2024 dpISA #407

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
vhscampos merged 4 commits into from
Jan 12, 2026
Merged

Add intrinsics for the new FP conversions introduced by the 2024 dpISA #407

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
f080ec7
Add intrinsics for the new FP conversions introduced by the 2024 dpISA
amilendra Aug 20, 2025
85c2698
Extend FP Single<->Double precision conversions to return results in …
amilendra Oct 8, 2025
42c3800
Merge branch 'main' into 2025-acle-fprcvt
Lukacma Jan 7, 2026
acbb839
Merge branch 'main' into 2025-acle-fprcvt
vhscampos Jan 12, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions main/acle.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -465,6 +465,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin

* Added feature test macro for FEAT_SSVE_FEXPA.
* Added feature test macro for FEAT_CSSC.
* Added support for FEAT_FPRCVT intrinsics and `__ARM_FEATURE_FPRCVT`.

### References

Expand Down Expand Up @@ -2207,6 +2208,13 @@ ACLE intrinsics are available. This implies that `__ARM_FEATURE_SM4` and
floating-point absolute minimum and maximum instructions (FEAT_FAMINMAX)
and if the associated ACLE intrinsics are available.

### FPRCVT extension

`__ARM_FEATURE_FPRCVT` is defined to `1` if there is hardware
support for floating-point to/from integer conversion instructions
with only scalar SIMD&FP register operands and results, and with
different input and output register sizes.

### Lookup table extensions

`__ARM_FEATURE_LUT` is defined to 1 if there is hardware support for
Expand Down Expand Up @@ -2590,6 +2598,7 @@ be found in [[BA]](#BA).
| [`__ARM_FEATURE_FP8DOT2`](#modal-8-bit-floating-point-extensions) | Modal 8-bit floating-point extensions | 1 |
| [`__ARM_FEATURE_FP8DOT4`](#modal-8-bit-floating-point-extensions) | Modal 8-bit floating-point extensions | 1 |
| [`__ARM_FEATURE_FP8FMA`](#modal-8-bit-floating-point-extensions) | Modal 8-bit floating-point extensions | 1 |
| [`__ARM_FEATURE_FPRCVT`](#fprcvt-extension) | FPRCVT extension | 1 |
| [`__ARM_FEATURE_FRINT`](#availability-of-armv8.5-a-floating-point-rounding-intrinsics) | Floating-point rounding extension (Arm v8.5-A) | 1 |
| [`__ARM_FEATURE_GCS`](#guarded-control-stack) | Guarded Control Stack | 1 |
| [`__ARM_FEATURE_GCS_DEFAULT`](#guarded-control-stack) | Guarded Control Stack protection can be enabled | 1 |
Expand Down
Loading