32-Bit Single-Cycle RISC-V Processor

A complete, single-cycle 32-bit RISC-V processor built from scratch in Verilog. This project implements a custom Harvard architecture with Memory-Mapped I/O (MMIO), custom hardware datapath upgrades for subroutines, and mathematically verified branch logic.

Designed and deployed on a Basys 3 Artix-7 FPGA running at a 10 MHz hardware clock.

🛠️ Hardware Specifications

• Architecture: 32-Bit Single-Cycle RISC-V (Harvard Architecture)
• Clock Speed: 10 MHz (Scaled down from 100 MHz via custom clock divider)
• Memory-Mapped I/O: * Address 512: Physical Basys 3 Switches (Input)
  • Address 256: Physical Basys 3 LEDs (Output)
• Instruction Support: Core ALU (ADD, SUB, AND, OR), Immediates (ADDI), Branching (BEQ, BNE), Memory (LW, SW), and Jumps (JAL, JALR).

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📁 Project Structure & Tasks

This repository is divided into three distinct phases of hardware and software development:

1. Task A: Baseline Hardware & Stack-Based Countdown

(Task_A_Baseline_Countdown) Demonstrates the baseline processor functionality before hardware upgrades.

• Application: A countdown timer that reads a seed value from the physical switches and decrements to zero on the LEDs.
• Software Delay Loop: Implements a nested delay loop utilizing strictly BEQ instructions to achieve a human-readable 0.8-second cycle at 10 MHz.
• Stack Management: Bypasses basic register storage by actively pushing the counter to Data Memory (initializing sp at address 128), loading it, decrementing, and saving it back to the stack on every cycle to validate the LW/SW datapaths.

2. Task B: Datapath Upgrades & Subroutine Implementation

(Task_B_Upgraded_CountUp) Upgrades the physical Control Unit and datapath routing to support modular software execution.

• New Instructions: Engineered support for JAL (Jump and Link), JALR (Jump and Link Register), and BNE (Branch if Not Equal).
• Application: A Count-Up timer that isolates the counting logic into an independent subroutine, utilizing JAL to save the return address and JALR to return to the polling state.
• Loop Optimization: Replaced clunky baseline BEQ loops with highly efficient BNE software delay loops.

3. Task C: Iterative Fibonacci Sequence

(Task_C_Fibonacci_Stack) A final, general-purpose application stressing the upgraded processor limits.

• Application: Calculates and displays the Fibonacci sequence continuously.
• Iterative Stack Architecture: Calculates the sequence not in registers, but by physically managing memory—pushing $F_{n-1}$ and $F_{n-2}$ to the stack, popping them to the ALU for addition, and pushing the new sum back to RAM at 10 million cycles per second.

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💡 Key Engineering Highlights

• Manual Branch Offset Calculation: All RISC-V B-type jump instructions were hand-calculated into exact 13-bit binary two's-complement formats to prevent Program Counter crashes and ensure flawless software loops.
• ALU Negative Immediate Fix: Identified and resolved a baseline architectural bug where I-type instructions with negative immediates (e.g., addi t2, t2, -1) defaulted to addition, fixed via direct ALUOp assignment in the Control Unit.

🚀 How to Run in Vivado

1. Clone this repository to your local machine.
2. Open Xilinx Vivado and create a new RTL Project for the Basys 3 board (Part: xc7a35tcpg236-1).
3. Add the Verilog files from the specific Task folder you wish to test as Design Sources.
4. Set TopLevelProcessor.v as the Top module.
5. Generate Bitstream and program the device.

👨‍💻 Author

Muhammad Abdullah Asim Computer Science Student