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AbhinavSD/README.md

Hi, I'm Abhinav

🎓 B.Tech ECE | College of Engineering Trivandrum

Interests:

  • RTL Design
  • ASIC Design
  • FPGA Development
  • RISC-V Processors
  • Network-on-Chip
  • AI Accelerators

Projects

Intelligent Predictive FIFO Custom RISC-V AI Processor AXI Multi-Channel DMA Controller

Tools

Verilog | Vivado | FPGA | TCL | Python | C

Currently Learning

  • Physical Design
  • Advanced Processor Architectures
  • NoC Design

Pinned Loading

  1. intelligent-predictive-fifo intelligent-predictive-fifo Public

    RTL implementation and verification of an Intelligent Predictive FIFO architecture in Verilog HDL.

    Verilog

  2. custom-risc-v-ai-processor custom-risc-v-ai-processor Public

    5-stage pipelined RISC-V processor with custom AI instructions, forwarding, hazard detection, and hardware acceleration extensions.

    Verilog

  3. memory-subsystem-design memory-subsystem-design Public

    Parameterized single-port and dual-port memory subsystem with arbitration, verification, and FPGA-ready RTL implementation.

    Verilog