💻 Computer Engineer Documenting my Projects/Learning
🔬 Design Lead @ ASICWRU — CWRU CHIPS ASIC Design
🧬 See the ASICs I've taped out: CWRU CPU · Tiny Pong
My interests are needle-felting, writing poetry/music, and baking! Outside of academics, you can catch me skateboarding around campus, playing chess, doing handstand push-ups, reading, or sleeping. 😁
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5-stage pipelined RISC-V processor with split L1 caches (direct-mapped I-cache, 2-way set-associative D-cache). Built from scratch and validated in SystemVerilog.
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Architected/led an underclassmen design team to implement a single-cycle RISC-V processor in Verilog and tape it out via Tiny Tapeout, targeting June 2026 submission.
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A Pong VGA controller taped out on SkyWater 130nm process via Tiny Tapeout. My first custom silicon tapeout project publicly available on GitHub.
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Designed, laid out, and manufactured a custom STM32F103 development board in KiCad 7.0 — from schematic to JLCPCB fabrication. Validated with a VHDL UART receiver on a Basys3 FPGA.
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A from-scratch C systems programming curriculum — shells, memory allocators, kernels, and device drivers — built as the software foundation underpinning the RISC-V superscalar SoC roadmap.
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A comprehensive, openly written guide to digital systems design — from logic gates to silicon. Built for CWRU students and anyone curious about hardware design, with the goal of making ASIC education accessible.
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