Interactive visualization tool for STA timing reports.
g2-timing-analysis transforms long textual timing reports into interactive visual timing paths, making timing debugging faster and easier.
Instead of manually reading long timing reports, users can explore timing paths visually through a web interface.
The following STA report formats are supported:
- Synopsys PrimeTime
- Synopsys Design Compiler (DC)
- Synopsys Fusion Compiler / ICC2
- Cadence Common UI
- Cadence Innovus (legacy format)
- The cause of timing violations are analyzed and shown in the Reason column
- You can control columns visibility by clicking Column in the toolbar
- Click a Reason entry to visualize the timing path graphically
- Use the star column in the "Path Group" table to focus on a specific path group for debugging
- Lightweight and easy to run
- No installation required
No installation is required. Simply download and extract the package.
tar zxvf g2-timing-analysis.tar.gz
cd g2-timing-analysis
./g2- Launch the program:
./g2- A browser window will open.
- Paste the file path of your STA timing report.
- Click Submit to start analyzing.
A sample timing report is included in the repository:
g2-timing-analysis/sample/pt.rpt
You can paste this file path into the tool to quickly try the visualization without preparing your own report.
g2-timing-analysis is part of the
G2 Chip Design AI Platform.
This tool is released as freeware and can be used without any license requirement.