Repository navigation
[Docs] Explain synchronous and asynchronous speculation timelines - #145
Merged
Merged
Conversation
Signed-off-by: bjf-frz <frz123db@gmail.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Purpose
Add a visual comparison of synchronous and asynchronous self-speculation to the speculation guide, before configuration instructions.
The timeline follows Round 0 and Round 1 across CPU, compute_stream and copy_stream. Matching acceptance/commit blocks, explicit start/end markers and a shared Round 1 completion guide show how later computation overlaps prior result delivery. R0–R3 denote recurrent depths. Timings, including slightly shorter GPU acceptance, are illustrative assumptions rather than measurements.
Includes editable SVG, 2× PNG, an offline viewer tab, implementation references, and links from README, architecture and scheduler documentation. Runtime and test code are unchanged.
Required human contributor answers
The following summarizes the contributor's explicit requirements and approval during the diagram review; private discussion is not reproduced. The final reviewed design is linked above.
1. What outcome are you trying to achieve?
Make synchronous versus asynchronous speculative execution understandable through a concrete timeline.
2. What is the highest-leverage variable for that outcome?
Visual correspondence: use the same time scale, matching operations and explicit round boundaries so readers can compare progress at the same instant.
3. How will this work move that variable rather than create busywork?
Show only two rounds, distinguish CPU/compute/copy activity, and align synchronous Round 1 completion with asynchronous completion. Keep a compact legend instead of another explanatory panel.
4. Who is the customer or user, and what do they actually need?
The contributor reviewing the inference architecture and readers of its documentation need to see dependencies, remaining waits and the source of cross-round overlap.
PR necessity and bugfix evidence
The contributor explicitly requested publishing the approved diagram and documentation as a PR for review. This is a documentation change, not a runtime bugfix.
Test Plan
vllm-rlt Version / Commit: base
e5e58c2b26df444b8494807ee4856309420c77e5; heade15cb76f340499214c2e441e750c7edcf1f14a23.git diff --check.pre-commit run --all-files.Test Result
tests/test_gsm8k_accuracy.py::test_run_refuses_the_stored_baseline_at_another_depth, reproduces on untouched basee5e58c2in the same environment. Importinglm_eval.models.hf_vlmsraisesAttributeError: module transformers has no attribute AutoModelForVision2Seq.