Skip to content
View Jujuakin's full-sized avatar

Block or report Jujuakin

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. 32-Bit-ALU 32-Bit-ALU Public

    32-bit Arithmetic-Logic Unit based on a hierarchical structure using VLSI

    Verilog

  2. EFDS EFDS Public

    Forked from parmounks/EFDS

    Python

  3. Pong-Game Pong-Game Public

    This project implements a classic two-player Pong game using Verilog HDL on the DE10-Lite FPGA board. The game logic is fully designed in hardware and displayed through the board’s VGA output.

    SystemVerilog

  4. Self-Automated-Plant-Watering-System Self-Automated-Plant-Watering-System Public

    This project implements a self-automated plant watering system using hardware components and Java programming. The system monitors soil moisture and automatically waters the plant when needed, whil…

    HTML