A comprehensive collection of 20 hands-on experiments demonstrating fundamental computer architecture concepts using the Ripes RISC-V simulator.
This repository serves as a complete laboratory curriculum for understanding pipelining, cache memory, hazards, branch prediction, memory management, and performance optimization in modern processors.
- Overview
- Getting Started
- Experiments by Category
- Repository Structure
- Prerequisites
- How to Use
- Learning Outcomes
- Contributing
- License
This repository contains RISC-V assembly programs designed to run in the Ripes simulator, providing visual and quantitative insights into how modern CPUs work. Each experiment includes:
- 📝 Detailed README with theory and setup instructions
- 🔧 Assembly code files (
.asm) ready to load in Ripes - 📊 Expected results and metrics to observe
- 🎯 Clear learning objectives
Download Ripes from the official repository:
- GitHub: https://github.com/mortbopet/Ripes
- Online Version: https://ripes.me
git clone https://github.com/JustineBijuPaul/ripes-projects.git
cd ripes-projects- Open Ripes
- Navigate to the Editor tab
- Load any
.asmfile from the experiments - Follow the README in each folder for specific setup instructions
| Experiment | Description | Key Concepts |
|---|---|---|
| Single-Cycle vs 5-Stage Pipeline Performance | Compare single-cycle and pipelined processors | CPI, Speedup, Pipeline stages |
| Pipeline Scheduling & Loop Unrolling | Optimize code to eliminate pipeline stalls | Loop unrolling, Instruction scheduling |
| Multi-Loop Pipeline Performance Study | Study nested vs flat loop performance | Control flow efficiency, Branch prediction pollution |
| Experiment | Description | Key Concepts |
|---|---|---|
| Pipeline Hazard Demonstration | Visualize RAW hazards and solutions | RAW hazards, Forwarding, Stalling |
| Load-Use Hazard Detection & Fixing | The critical load-use hazard problem | Load-use hazard, Hardware vs software solutions |
| Arithmetic Program Optimization | ALU-to-ALU forwarding demonstration | Data forwarding, Dependency chains |
| Control vs Data Hazard Impact Study | Quantify hazard contributions separately | Hazard isolation, Performance analysis |
| Branch Delay Penalty Study | Control hazards and branch penalties | Pipeline flush, Branch prediction |
| Function Call Overhead Analysis | Cost of function calls in pipelines | JAL/JALR, Stack frames, Control hazards |
| Experiment | Description | Key Concepts |
|---|---|---|
| Cache Block Size Impact on Miss Rate | Effect of block size on cache performance | Spatial locality, Block size trade-offs |
| Cache Mapping Technique | Direct-mapped vs set-associative caches | Conflict misses, Associativity |
| Array Size Vs Cache Miss Analysis | Cache thrashing with matrix multiplication | Working set, Thrashing, Loop tiling |
| Instruction Vs Data Cache Performance | I-Cache vs D-Cache behavior | Harvard architecture, Cache pressure |
| Experiment | Description | Key Concepts |
|---|---|---|
| Memory Locality Performance Study | Sequential vs random access patterns | Spatial locality, Temporal locality |
| Alignment Impact on Memory Performance | Aligned vs misaligned memory access | Memory alignment, Exception handling |
| Stack Vs Heap Memory Access Speed Test | Stack locality vs heap fragmentation | Stack frames, Pointer chasing |
| TLB Impact on Memory Access Time | TLB thrashing and page table walks | Virtual memory, TLB, Page faults |
| Page Fault Experimentation Using Virtual Memory | Trap handling and page fault recovery | Exceptions, CSRs, Trap handlers |
| Experiment | Description | Key Concepts |
|---|---|---|
| Static Branch Prediction Analysis | Compare static prediction strategies | Always-taken, BTFNT, Misprediction rate |
| Experiment | Description | Key Concepts |
|---|---|---|
| String Handling Performance | SWAR-optimized string operations | SIMD, Word-wise processing, Alignment |
ripes-projects/
├── README.md # This file
├── Alignment Impact on Memory Performance/
│ ├── README.md
│ └── aligned_vs_misaligned.asm
├── Arithmetic Program Optimization/
│ ├── readme.md
│ └── dependency_chain.asm
├── Array Size Vs Cache Miss Analysis/
│ ├── README.md
│ ├── matmul_naive.asm
│ └── matmul_tiled.asm
├── Branch Delay Penalty Study/
│ ├── readme.md
│ └── count_evens.asm
├── Cache Block Size Impact on Miss Rate/
│ ├── README.md
│ └── sequential_traversal.asm
├── Cache Mapping Technique/
│ ├── README.md
│ └── conflict_access.asm
├── Control vs Data Hazard Impact Study/
│ ├── readme.md
│ ├── hazards_combined.asm
│ └── hazards_control_only.asm
├── Function Call Overhead Analysis/
│ ├── readme.md
│ ├── func_call.asm
│ └── func_inline.asm
├── Instruction Vs Data Cache Performance/
│ ├── README.md
│ ├── icache_pressure.asm
│ └── dcache_pressure.asm
├── Load-Use Hazard Detection & Fixing/
│ ├── readme.md
│ ├── hazard_demo.asm
│ └── hazard_fixed.asm
├── Memory Locality Performance Study/
│ ├── README.md
│ ├── sequential_access.asm
│ └── random_access_lcg.asm
├── Multi-Loop Pipeline Performance Study/
│ ├── readme.md
│ ├── nested_loop.asm
│ └── flat_loop.asm
├── Page Fault Experimentation Using Virtual Memory/
│ ├── README.md
│ └── page_fault_demo.asm
├── Pipeline Hazard Demonstration/
│ ├── README.md
│ ├── raw_hazards.asm
│ └── manual_stalls.asm
├── Pipeline Scheduling & Loop Unrolling/
│ ├── readme.md
│ ├── Naive_Loop.asm
│ └── optimized_loop.asm
├── Single-Cycle vs 5-Stage Pipeline Performance/
│ ├── readme.md
│ └── sum_loop.asm
├── Stack Vs Heap Memory Access Speed Test/
│ ├── README.md
│ ├── stack_access.asm
│ └── heap_access.asm
├── Static Branch Prediction Analysis/
│ ├── readme.md
│ └── branch_analysis.asm
├── String Handling Performance/
│ ├── README.md
│ ├── strcpy_naive.asm
│ └── strcpy_swar.asm
└── TLB Impact on Memory Access Time/
├── README.md
└── tlb_thrash.asm
- Ripes Simulator (v2.0 or later recommended)
- Basic understanding of assembly language
- Familiarity with computer architecture concepts
- CPU pipeline stages (IF, ID, EX, MEM, WB)
- Cache memory hierarchy
- RISC-V instruction set basics
- Basic understanding of hazards and stalls
- Start with Pipeline Basics: Begin with "Single-Cycle vs 5-Stage Pipeline Performance" to understand the fundamental differences
- Progress to Hazards: Move through the hazard experiments to understand why pipelines stall
- Explore Cache Memory: Learn how memory hierarchy affects performance
- Advanced Topics: Tackle branch prediction and optimization experiments
Each experiment is designed as a standalone lab that can be:
- Assigned as homework with the README as a guide
- Used for in-class demonstrations
- Extended with custom parameters and analysis questions
1. Read the experiment's README.md
2. Configure Ripes as specified
3. Load the .asm file(s)
4. Run the simulation
5. Collect metrics (Cycles, CPI, Cache hits/misses)
6. Analyze and compare results
7. Document findings
After completing these experiments, you will be able to:
- ✅ Explain the 5-stage RISC-V pipeline operation
- ✅ Identify and resolve data hazards (RAW, WAR, WAW)
- ✅ Understand forwarding and stalling mechanisms
- ✅ Calculate CPI and speedup metrics
- ✅ Configure and analyze cache behavior
- ✅ Understand spatial and temporal locality
- ✅ Compare different cache mapping techniques
- ✅ Optimize code for cache performance
- ✅ Understand virtual memory concepts
- ✅ Analyze TLB behavior and page faults
- ✅ Recognize memory alignment importance
- ✅ Apply loop unrolling and scheduling techniques
- ✅ Minimize branch mispredictions
- ✅ Write cache-friendly code
- ✅ Understand function call overhead
| Metric | Description | Where to Find |
|---|---|---|
| Cycles | Total clock cycles executed | Statistics panel |
| Instructions | Total instructions retired | Statistics panel |
| CPI | Cycles Per Instruction | Statistics panel |
| Cache Hits | Successful cache accesses | Cache statistics |
| Cache Misses | Cache access failures | Cache statistics |
| Hit Rate | Hits / Total accesses | Cache statistics |
| Pipeline Bubbles | Stall cycles inserted | Pipeline visualization |
Contributions are welcome! Please feel free to:
- Report Issues: Found a bug or have a suggestion? Open an issue
- Add Experiments: Create new experiments following the existing format
- Improve Documentation: Help clarify explanations or add examples
- Fix Bugs: Submit pull requests for any corrections
- Follow the existing folder structure
- Include a comprehensive README with each experiment
- Test all assembly code in Ripes before submitting
- Document expected results and metrics
- Ripes Simulator
- RISC-V Specification
- Patterson & Hennessy - Computer Organization and Design: RISC-V Edition
- Hennessy & Patterson - Computer Architecture: A Quantitative Approach
The MIT License (MIT)
Copyright (c) 2025 Justine Biju Paul
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- Ripes Development Team for creating an excellent educational simulator
- RISC-V Foundation for the open instruction set architecture
- All contributors and students who have helped improve these experiments
Happy Learning! 🎓
Understanding computer architecture one pipeline stage at a time.