🔀 1x3 Router Verification — UVM Testbench

A complete Universal Verification Methodology (UVM) based functional verification environment for a 1-input, 3-output (1x3) packet router design.

📌 Overview

This project implements a structured UVM testbench to verify the functional correctness of a 1x3 router RTL design. The router accepts packets on a single input port and routes them to one of three output ports based on the address field in the packet header.

🧩 Verification Architecture

• UVM Environment — Top-level env integrating all agents and scoreboard
• Input Agent — Driver + Monitor + Sequencer for the input port
• Output Agents (x3) — Monitors on each of the 3 output ports
• Scoreboard — Checks routing logic and data integrity
• Coverage Collector — Functional coverage for routing paths and packet types
• Sequences & Tests — Directed and constrained-random test scenarios

✅ Test Scenarios

• Reset and initialization check
• Packet routing to all three output ports
• Back-to-back packet transfers
• FIFO full and overflow conditions
• Error packet handling
• Constrained random regression

🛠️ Tools & Technologies

• Language: SystemVerilog
• Methodology: UVM 1.2
• Simulator: QuestaSim / VCS / Xcelium

📁 Project Structure

Project Structure

1x3_router_uvm/
├── rtl/                          # Design Under Test (DUT)
│   └── router.sv                 # 1x3 router RTL
│
├── tb/                           # UVM Testbench
│   ├── env/
│   │   └── router_env.sv         # Top-level UVM environment
│   │
│   ├── src_agent/                # Source-side agent (active)
│   │   ├── src_agent.sv          # UVM agent wrapper
│   │   ├── src_driver.sv         # Drives packets into DUT
│   │   ├── src_monitor.sv        # Observes input port
│   │   └── src_sequencer.sv      # Sequencer for source
│   │
│   ├── dest_agent/               # Destination-side agent (passive, x3)
│   │   ├── dest_agent.sv         # UVM agent wrapper
│   │   ├── dest_monitor.sv       # Observes output ports 0, 1, 2
│   │   └── dest_sequencer.sv     # Sequencer for destination
│   │
│   ├── seq/                      # Sequences & transactions
│   │   ├── router_seq_item.sv    # Base transaction (packet)
│   │   ├── src_sequences.sv      # Source-side sequences
│   │   └── dest_sequences.sv     # Destination-side sequences
│   │
│   ├── scoreboard/
│   │   └── router_scoreboard.sv  # Checks routing correctness
│   │
│   ├── coverage/
│   │   └── router_coverage.sv    # Functional coverage groups
│   │
│   └── test/                     # Test classes
│       ├── router_base_test.sv   # Base test (extended by all)
│       ├── src_test.sv           # Source-side directed tests
│       └── dest_test.sv          # Destination-side tests
│
├── sim/                          # Synopsys VCS simulation scripts
│   ├── Makefile                  # compile & run targets
│
├── .gitignore                    # Excludes simv, csrc/, *.log
└── README.md                     # This file

🚀 How to Run

cd sim/
make run TEST=router_base_test