Add PYNQ-Z2 port (pynq/ subdir)

[AbdullahAlNafisah]

Self-contained port of TALOS-V2 to the Xilinx PYNQ-Z2 (Zynq-7020 XC7Z020CLG400-1). The original Intel DE1-SoC flow at the repository root is unchanged; the new pynq/ subdirectory adds an alternative build that runs the unmodified microgpt_exact_core RTL through Vivado 2024.1 + the PYNQ runtime instead of Quartus + the JTAG-Avalon bridge.

Both flows coexist — users with either board can build and run from a single clone. Verified end-to-end: bitstream loads via pynq.Overlay, AXI4-Lite slave at 0x4000_0000 advertises MAGIC='MGRT', generation loop produces 8 tokens per call.

Contents of pynq/:

• hw/src/core/ + hw/ip/ — files byte-identical to upstream rtl/, redistributed under Apache-2.0 so the Vivado build is self-contained. One file modified for Vivado INCLUDE_DIRS: hw/src/core/include/microgpt_exact_core_rom_init.svh (paths only).
• hw/src/top/microgpt_pynq_top.sv — new AXI4-Lite slave wrapper exposing the upstream core via the Zynq PS GP0 master.
• hw/tcl/build.tcl — new Vivado batch build (Zynq + AXI Interconnect
  • microgpt_pynq_top + LD0..LD3 constraints).
• hw/sim/cocotb/ — new cocotb regression suite for the AXI wrapper.
• sw/drivers/microgpt.py — new Python driver (pynq.MMIO + UIO IRQ fast path).
• sw/notebooks/ — demo, hardware-advantage, throughput notebooks.
• tutorials/ — workflow walkthrough notebooks.
• overlays/microgpt.{bit,hwh} — pre-built bitstream artefacts targeting xc7z020clg400-1.

Per-file attribution: pynq/UPSTREAM.md.
Licensing: pynq/LICENSE.original (BSD 3-Clause for new work). NOTICE updated with the new copyright line.