[pull] main from llvm:main - #1669
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#210618) This mirror's the PIE's CHECK lines, which were already stricter. --- <sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
Firstly, the nopic test had an unused HEX check line when it should have been checking .got.plt, and the pic test was only checking .got2, also ignoring .got.plt. Secondly, the indentation for instructions was inconsistent within a single file. Thirdly, neither test was actually checking the code for func's IPLT entry in .glink, only that the symbol existed as a normal function that wasn't the same as the resolver, and the nopic test wasn't even testing the full contents of the PLT call stub, which was inconsistent with the pic test. Fourthly, the pic test used the same output file for two different links, which can be confusing when debugging. Finally, the comment at the start of the pic test's PLT call stub had no bearing on the immediate in use, instead being the same as the nopic's one with the 4 subtracted from both sides (presumably trying to account for the nopic test not having the extra .got2 entry, but neglecting the fact that it's not using absolute addressing, and even if it were, the addresses are entirely different). --- <sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
…#211289) A WebAssembly function begins with a local variable declaration header that is part of the function but is not an executable instruction. A breakpoint at a raw function start, such as one added by a scripted resolver, landed on the header and could never be hit. Name and file-and-line breakpoints already move past it, because that is handled at the line-table level. The disassembler already skipped this header inline. Move that logic behind a new Architecture:: SkipFunctionHeader hook, implemented by a new WebAssembly architecture plugin, and call it from both the disassembler and Breakpoint::AddLocation so any breakpoint resolves to the first instruction.
…of (#211628) `CUFPredefinedVarToGPU` rewrites references to the predefined CUDA builtins (`threadidx`/`blockidx`/`blockdim`/`griddim`) into GPU special-register reads. For each predefined-var `fir.declare` it also erased the declare's backing `fir.address_of`. That assumed every declare owns a private `address_of`, which is only true before CSE. Once a single `fir.address_of` of a builtin is shared by several `fir.declare`s — e.g. after a `device` routine is inlined into a `global` kernel and CSE coalesces the duplicated `address_of` ops — the pass queued that one op for deletion once per declare and erased it while another declare still used it, thus aborting compilation with `'fir.address_of' op operation destroyed but still has uses` error. With this PR, the backing ops are collected into a de-duplicated set and erased after all predefined declares are gone, and only when `use_empty()`. This makes the deletion safe regardless of how many declares share an `address_of`, and leaves it untouched if any other user remains.
This would warn whenever using a triple that isn't for the host architecture. Other tools don't do this. Copy what llc does and default to no cpu.
Implement the conversion to atomic int pointer through temp alloca
Reviewers: Pull Request: #211635
Add Clang IR coverage for `#pragma weak alias = target` on Darwin. The test verifies that Clang: - emits the alias with weak linkage; - keeps calls referencing the alias instead of replacing them with the aliasee. This is a test-only follow-up to #198148 and covers the Clang lowering path used by #111321.
Alternative to #201772. When SelectionDAG expands a small memcpy/memmove/memset it can raise the alignment of the destination stack object, but only when the destination is a bare FrameIndex. Since #121710, NVPTX treats allocas as assumed-local, and InferAddressSpaces rewrites the intrinsic operands to addrspacecasts. ISel no longer sees the frame index, the alignment isn't raised, and small unaligned copies are expanded byte-by-byte. We observed up to 1.9x slower kernels in JuliaGPU/CUDA.jl#3162. #201772 fixed this in SelectionDAG by looking through addrspacecasts to recover the stack object. Per review feedback there, this PR takes a different approach: NVPTXLowerAlloca now turns each generic alloca into an equivalent addrspace(5) alloca plus one cast back to the generic address space for existing users. The normal InferAddressSpaces pass then propagates the local address space into loads/stores and folds the cast away where possible. At -O0, the cast remains, but the underlying frame object is still local, so stack lowering addresses it correctly. Making allocas actually local requires NVPTX stack lowering changes: - eliminateFrameIndex resolves addrspace(5) frame indices against the local frame pointer %SPL. Previously every frame index used the generic %SP, which mis-addresses local stores and double-converts escapes. - LowerDYNAMIC_STACKALLOC returns the local pointer instead of always casting to generic when the requested result type is already local. NVPTX still declares the alloca address space as 0, so allocas are generic by default and the pass must enforce locality, including at -O0. This PR is compatible with making the DL actually put allocas in AS5: the stack-lowering changes (%SPL frame indices, local LowerDYNAMIC_STACKALLOC) are needed regardless of how an alloca became local and stay correct under A5, while the scaffolding that only enforces the invariant becomes unnecessary and can be dropped. cc @arsenm --------- Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
…0807) Getting the process info from ProcessELFCore would always return the information from the prpsinfo.pr_psargs from the NT_PRPSINFO. This meant if the process was launched with a symlink, the process info would always claim the main executable was the symlink. We want the process info's executable to always be the resolved executable when possible. The DynamicLoaderPOSIXDYLD was using the process info to load the main executable if it wasn't set, or it was comparing if the main executable's module spec matched the process info, and if it didn't match it would end up trying to load the main executable using the process info. We also ask for the UUID from the process before trying to use the process info to replace the executable in DynamicLoaderPOSIXDYLD::ResolveExecutableModule().
…tors (#211153) Sequential `gpu_block_redundant` ancestors need selective launch-dim handling in `getAncestorParDims`: including them always widens gang-private to per-thread; omitting them always can predicate block-redundant bodies on `blockIdx` after partition. Include launch dims when the block-redundant loop is worksharing or is the innermost parallel parent; skip them for an outer sequential block-redundant wrapper around nested worksharing.
These are tests added after the recent batch migration to new triples.
…plate instantiation (#210610) Fixes #210234 As per my investigation (mostly following stack traces and dumping variable values), a default empty `DeclarationNameInfo` was being returned after template substitution [over here](https://github.com/llvm/llvm-project/blob/c45b4e4d00bed488d6ece5608560561732ae5b9e/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp#L3270). ```cpp // D-.>getNameInfo() has actual data here DeclarationNameInfo NameInfo = SemaRef.SubstDeclarationNameInfo(D->getNameInfo(), TemplateArgs); // NameInfo has default values ``` This was being passed on directly to `CXXDestructorDecl::Create` leading to the assertion being hit. This PR adds a check that ensures `NameInfo` actually contains a valid destructor name before constructing a `CXXDestructorDecl`. This fixes the assertion being hit in the reproducer from the linked issue.
This new CFI directive directly assigns an RA signing state to the RA_SIGN_STATE DWARF pseudo-register for use when unwinding, to indicate whether the value of PC has been used as a diversifier for return address signing. The new directive subsumes and replaces .cfi_negate_ra_state_with_pc, which was found to be unsuitable for descibing some block layouts [1], particularly in hot-cold-split functions. 1: ARM-software/abi-aa#346
…behaviour as ffast-math (#208709) Previously when using `-cl-fast-relaxed-math` flag along with `fhonor-nans` or `fhonor-infinities` the honor flags did not override the relaxed math flag. This behaviour is something that is not seen in case of ffast-math for general targets. This patch makes adjustments to how the driver and cc1 handles the relaxed math flag for opencl. The flag was in the path of `fast-math` so when someone used the `-cl-fast-relaxed-math` flag they were ultimately overriding everything with fast-math. This was the main reason why honor flags were not overriding relaxed math (atleast that's what I have understood from my time working on this). I have added tests for this as well and modified CodeGen cc1 tests according to the changes in the patch. I have personally not tested this on any AMD targets myself yet. So I am unsure about this breaking anything (hopefully it should rather fix). closes #178514
…1148) Use `LIBC_NO_SANITIZE_OOB_ACCESS` for small SIMD helper functions (load/store/gather/scatter/expand/compress). Even though the actual functions which have logical OOB reads (such as `clang_vector::string_length`) already have `LIBC_NO_SANITIZE_OOB_ACCESS` attribute to ignore OOB reads, it's not enough - as we see downstream reports from ASan builds of llvm-libc (using tip-of-trunk Clang), both with `-O1` and `-O2`. We simply can't rely on the SIMD helpers being inlined into the caller function, with their memory reads/writes ignored. Thus, apply the `no_sanitize` attribute to the helpers themselves. This is clearly suboptimal, as we're effectively disabling sanitizer checks for *all* the code using SIMD to read/write from memory, but it seems to be the easiest reasonable fix. After all, code using SIMD (like code using explicit intrinsics or inline assembly) should be written only in special cases, with author knowing what they're doing.
Docs for AMDGPU instruction syntax under llvm/docs/AMDGPU are being moved out of LLVM. They can be found at the [ROCm LLVM Compiler Infrastructure website](https://rocm.docs.amd.com/projects/llvm-project/en/latest/index.html)
…ation (gcc 7.5.0) (#211331) GCC 7.5.0 fails to compile this code. Use explicit upcasts from std::unique_ptr<Derived> to std::unique_ptr<Base> in deserializeSummary and deserializeAnalysisResult. This resolves a compilation error where llvm::Expected<std::unique_ptr<Base>> could not be constructed from unique_ptr of derived summary/result types.
…M pipeline (#210539) Add convert-vector-to-xegpu (nested under gpu.module) to lower kernel-side vector ops to XeGPU. Move convert-vector-to-scf from the pre-GPU common pipeline into the post-GPU pipeline, so host transfer ops (and any SCF the pass emits) are lowered to loops before the vector-to-LLVM conversion. --------- Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Migrate cases by script that don't fail
InnerLoopVectorizer stored a LoopVectorizationCostModel pointer (Cost) but all users have been removed.
…tElementInsts (#211414) When building vectors from multiple scalars in a loop, allow the insertions using invariant data to be hoisted, even if blocked by the variant insertions. In the SLP vectorizer, c1b37eacbf makes the assumption that these build vectors will properly be hoisted, when they are not leads to regressions such as #195497. Reland of #200532. Assisted By: Codex Co-authored-by: Luke Lau <luke_lau@icloud.com> Co-authored-by: Nikita Popov <github@npopov.com>
…ified memory. (#211650) OpenACC declare globals may already exist in the GPU module from earlier GPU lowering. Under unified memory, this pass expects those device copies as declarations, but a pre-existing global may still have an initializer and therefore not match. This change adapts an otherwise equivalent existing GPU global to declaration form and reuses it; A lit test covers a host/GPU declare global that should be reused as a declaration in the GPU module.
…ng (#211651) `ACCLoopTiling` used to lower an N-dimensional `tile()` clause by *uncollapsing* the fused loop into a deep nest of single-IV `acc.loop`s (`tile_1 → … → tile_N → elem_1 → … → elem_N`). This discards the natural grouping of the tile clause: the 2N single-IV loops no longer express "these are the tile iterations" and "these are the in-tile iterations" as collapsible units, and gang/vector end up spread across a deep nest where only the outermost loop of each group carries the attribute. This could potentially lead to poor parallelism assignment. With this MR: `tileACCLoops` now rewrites the single fused `acc.loop` in-place into exactly two multi-IV loops, each carrying all the tiled induction variables: - a **tile-group** loop whose steps are the original steps scaled by the tile sizes, and - a nested **element-group** loop that walks the iterations within one tile, with upper bounds clamped to `min(origUB, tileStart + tileExtent)`. Keeping each group as a single multi-IV `acc.loop` preserves the tile/element structure as two collapsible units instead of a 2N-deep single-IV nest, which is a simpler canonical form. The gang/worker/vector distribution across the two groups is unchanged from before. This change also diagnoses `tile` + `collapse` on the same loop because these clauses give conflicting loop-association counts. The pass now emits a NYI diagnostic instead of silently dropping the `collapse` clause. Added a new invalid-input test to verify this. With the pass no longer uncollapsing, `uncollapseLoops` and the vector-of-loops `tileACCLoops(SmallVector<LoopOp>&, …)` overload (and the now-orphaned `createInnerLoop` helper) are deleted, along with their unit tests. New unit tests are added to cover the surviving fused-loop overload.
Extend the vector.transfer_read/transfer_write lowerings so they can produce N-D xegpu.load_nd/store_nd, not just 1D/2D, and relax the out-of-bounds handling to match load_nd's implicit-zero padding. Restructure both patterns as "block first, then scatter as fallback. --------- Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
…11600) Remove an unnecessary level of indirection.
ASan emits a symbol for a static global in `TestTransformation.cpp` that
causes link issues in green dragon.
Added `__attribute__((no_sanitize("address")))` to that static global to
fix the test.
rdar://182623740
This fixes 4a6858a (#210527). Buildkite error link: https://buildkite.com/llvm-project/upstream-bazel/builds?commit=4a6858aecce9a6a570ea12f655aa513f73ab20f6 Co-authored-by: Google Bazel Bot <google-bazel-bot@google.com>
Removed the accindentally commented out code, causing regressions with ordered reductions Reviewers: Pull Request: #211662
…206210) Just like explicit sections. We were seeing globals with implicit sections marked large under the medium code model. Reland of #204247, with a fix to not crash on declarations with an explicit section. Implicit sections are not applied to declarations, so don't check isDeclarationForLinker() globals for implicit sections. Assisted-by: Gemini
The parallel linker's getODRAttributes() did not list `DW_AT_LLVM_alloc_type`, so the dependency tracker treated it as a live reference rather than a type reference. A type reachable only through DW_AT_LLVM_alloc_type was therefore never kept: the enclosing subprogram is marked live, and its type-table-candidate children are skipped during live marking on the assumption they are retained through the type path. The attribute then resolved to offset 0, landing on the compile unit header, which got correctly caught by the DWARF verifier. The classic linker already lists `DW_AT_LLVM_alloc_type` in isODRAttribute(), so this PR restores parity between the two. Assisted-by: Claude rdar://182715403
Re-generate test checks to reduce diff for upcoming PR.
Example:
```fortran
!$acc parallel loop collapse(2) num_gangs(10) reduction(+:a)
do i = 1, n
do j = 1, n
do k = 1, m
a(k) = a(k) + x(k,i) * y(k,j)
end do
end do
end do
```
In this code, ACCCG pads ThreadX to the subgroup size because
`gpu.all_reduce` uses subgroup shuffles. This unnecessarily increases
private reduction storage when only one Y/Z row is active.
Fix: preserve partial ThreadX launches for a single row, while retaining
alignment when Y/Z rows could share a subgroup.
Users and tools sometimes need to know which C++ standard library Clang selected, and which include directories the driver added for it. Today they have to inspect verbose or `-###` output. Add options to print this information directly: `--print-cxx-stdlib` `--print-cxx-stdlib-include-dirs` For MSVC targets, the default printed library is `msvcstl`. Explicit `-stdlib=` values are still reported as requested. The include-dir query reuses toolchain logic, including the MSVC STL include path for the default MSVC case.
During compute lowering, also set the collapse count attribute when creating scf.parallel ops from acc.loop ops. While this collapse count is implied by the number of IVs, later canonicalizations may use this information to decide whether or not to collapse the loop nest further
…lass` pass (#211147) Added the `class-name-format` option that takes a format string used to generate the wrapper class name. This provides greater control over the generated `ClassOp` name. When multiple identically structured IR files need to be programmatically lowered with this pass and linked, there will be naming conflicts which this patch provides a method of resolution for.
Finds calls to `value_or` (and alternative spellings `valueOr`, `ValueOr`) on optional types where the return type is expensive to copy. Objects not trivially copyable, or larger than a configurable size threshold are treated as expensive. Rationale: While `value` and `operator*` return references, `value_or` for these types always returns by value.
…209389) ### summary part of : #185382 lower all intrinsics in : https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-right-and-narrow
…211495) The documentation for qSpeedTest says ``` send packet: qSpeedTest:response_size:response-size; read packet: data:<response data> response-size is a hex encoded unsigned number up to 64 bits in size. ``` debugserver implements qSpeedTest as per this documentation, but lldb sends the number in decimal (base 10), and lldb-server parses it as base 10. I changed lldb and lldb-server to base 16. This is a maintenance command used by lldb developers exclusivley, so IMO I'm not handling a migration for old/new servers or defining a new packet or key. I was running some packet transmission tests with debugserver and noticed debugserver was sending much larger packets than requested; that's the kind of failure you see when there is a mismatch. I audited all uses of `getAsInteger()` that pass a 0 for the radix, meaning auto-detect the radix, in the gdb-remote dir and changed nearly all of them to specify either base 10 or base 16. There were two places where we were using auto-sensing on a base 16 number (and no "0x" prefix), which would parse incorrectly if an [a-f] letter did not occur. There is one use of `getAsInteger(0,...)` that is still in place, for pasing the `qRegisterInfo` eh-frame/dwarf register numbers. Our documentation for these keys specifies that they may be base 10 or base 16 if prefixed with 0x. This is unlike anywhere else in gdb remote serial protocol, and smells like something I probably stuck in there 15+ years ago because I've never liked the ambiguity about number bases in the protocol and I made this half-hearted stab at encouraging use of "0x". It is always fun to see the inconsistencies as you review multiple packets. qProcessInfo returns keys like pid/gid/ppid in base 16. qfProcessInfo returns the same keys in base 10. qHostInfo returns cputype/cpusubtype (a Mach-O way of specifying a target cpu) in base 10, qProcessInfo returns the same keys in base 16. There's so many of these kinds of little inconsistencies :/
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