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Preserve inline source scopes in line-table debug info - #1582

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tpn:codex/coop-interop-inline-lineinfo
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Preserve inline source scopes in line-table debug info#1582
tpn wants to merge 2 commits into
NVIDIA:mainfrom
tpn:codex/coop-interop-inline-lineinfo

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@tpn tpn commented Oct 21, 2026 •
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Line-table builds currently lose inline call chains because the MIR importer retains source scopes only for full debug info. Keep those scopes whenever line tables are enabled, so the existing exporter can emit inline attribution. Off mode and variable-debug gates keep their behavior.

This is a standalone change on current main: one production-line change and its importer/lowering regression, with no collective-checker or storage-planner prerequisite.

Validation: the regression fails with the old gate and passes with the fix; all 1,180 importer tests, strict importer Clippy and formatting pass. The 26 existing exporter debug tests also pass. An unchanged native example shows restored LLVM inline chains and surviving nested CUBIN attribution; baseline and candidate both pass its 12-value GPU check.

The example's final SASS differs (184 → 200 instruction slots), with 19 registers and no stack/local storage in both builds. Some helper locations disappear during optimization. This does not establish performance equivalence or debugger stepping. All 55 published-head CI checks pass.

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@tpn tpn mentioned this pull request Oct 21, 2026
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@nihalpasham nihalpasham added cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book codegen Device code-generation pipeline (Rust MIR to IR to PTX) llvm-export Textual LLVM/NVVM IR exporter (llvm-export crate) debug info Debug information in generated PTX/IR (line/source maps) bug Something isn't working Depends Blocked on another PR/issue or an upstream dependency labels Oct 21, 2026
@tpn
Preserve inline scopes in line-table debug info
ac90d9e 
Retain the source-scope map when line tables are enabled so native
debug metadata includes inline call chains without variable debug info.

Signed-off-by: Trent Nelson <trent@trent.me>
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tpn force-pushed the codex/coop-interop-inline-lineinfo branch from ffa3f2e to ac90d9e Compare October 22, 2026 04:39
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@tpn tpn mentioned this pull request Oct 23, 2026
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@elibol
test(oxide): validate inline source scopes against current main
bec608b 
Integrate current main and its pinned stable compiler. Revalidate importer regressions, optimized cooperative-groups GPU execution, and before/after generated machine instructions.

Signed-off-by: Melih Elibol <1884921+elibol@users.noreply.github.com>
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elibol commented Oct 26, 2026

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/ok to test bec608b

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elibol commented Oct 26, 2026

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Updated to bec608b8da8f3bc670ee265a62720c16b9ee1a38 by merging current main.

All 1,214 importer tests and strict importer Clippy pass. cargo oxide run coop_groups_demo --arch sm_120 --lineinfo passes on RTX 5090/CUDA 13.3. Reverting only the inline-scope gate and rebuilding/rerunning that example produces identical SASS instruction streams for all 22 kernels. The candidate source was restored afterward. This validates that workload; it is not a universal performance claim.

CI's example compilation and other completed checks pass; Rust CodeQL is still running. Included as a v0.5.0 debugging/interop candidate in #1606 and draft #1613, separately from the Tile compiler fixes and debugger resolver.

This was referenced Oct 26, 2026
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elibol marked this pull request as ready for review October 26, 2026 20:13
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elibol requested a review from nihalpasham as a code owner October 26, 2026 20:13

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bug Something isn't working codegen Device code-generation pipeline (Rust MIR to IR to PTX) cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book debug info Debug information in generated PTX/IR (line/source maps) Depends Blocked on another PR/issue or an upstream dependency llvm-export Textual LLVM/NVVM IR exporter (llvm-export crate)

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