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evbarm/am18: add interrupt controller
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‎sys/arch/arm/ti/am18xx_intc.c‎

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/* $NetBSD $ */
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/*-
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* Copyright (c) 2025 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Yuri Honegger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Interrupt controller for the TI AM18XX SOC
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*/
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#define _INTR_PRIVATE
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#include <sys/cdefs.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <dev/fdt/fdtvar.h>
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#include <arm/armreg.h>
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#include <arm/pic/picvar.h>
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struct am18xx_intc_softc {
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struct pic_softc sc_pic;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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int sc_num_irqs;
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};
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static int am18xx_intc_match(device_t, cfdata_t, void *);
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static void am18xx_intc_attach(device_t, device_t, void *);
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static void am18xx_intc_unblock_irqs(struct pic_softc *, size_t, uint32_t);
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static void am18xx_intc_block_irqs(struct pic_softc *, size_t, uint32_t);
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static void am18xx_intc_establish_irq(struct pic_softc *,
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struct intrsource *);
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static void am18xx_intc_set_priority(struct pic_softc *, int);
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static void am18xx_intc_irq_handler(void *);
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static void *am18xx_intc_fdt_establish(device_t, u_int *, int, int,
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int (*)(void *), void *,
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const char *);
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static void am18xx_intc_fdt_disestablish(device_t, void *);
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static bool am18xx_intc_fdt_intrstr(device_t, u_int *, char *, size_t);
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static void am18xx_intc_enable_interrupts(struct am18xx_intc_softc *);
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#define AM18XX_AINTC_CR 0x4
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#define AM18XX_AINTC_GER 0x10
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#define AM18XX_AINTC_SECR1 0x280
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#define AM18XX_AINTC_ESR1 0x300
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#define AM18XX_AINTC_ECR1 0x380
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#define AM18XX_AINTC_CMR0 0x400
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#define AM18XX_AINTC_HIER 0x1500
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#define AM18XX_AINTC_GER_ENABLE 1
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#define AM18XX_AINTC_HIER_IRQ 2
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#define AM18XX_AINTC_IRQ_CHANNEL 4 /* any number between 2 and 31 works */
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#define INTC_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)
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#define INTC_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)
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#define PICTOSOFTC(pic) \
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((struct am18xx_intc_softc *) \
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((uintptr_t)(pic) - offsetof(struct am18xx_intc_softc, sc_pic)))
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static struct am18xx_intc_softc *intc_softc;
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CFATTACH_DECL_NEW(am18xxintc, sizeof(struct am18xx_intc_softc),
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am18xx_intc_match, am18xx_intc_attach, NULL, NULL);
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "ti,cp-intc" },
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DEVICE_COMPAT_EOL
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};
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static const struct fdtbus_interrupt_controller_func am18xx_intc_fdt_funcs = {
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.establish = am18xx_intc_fdt_establish,
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.disestablish = am18xx_intc_fdt_disestablish,
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.intrstr = am18xx_intc_fdt_intrstr,
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};
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static const struct pic_ops am18xx_intc_picops = {
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.pic_unblock_irqs = am18xx_intc_unblock_irqs,
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.pic_block_irqs = am18xx_intc_block_irqs,
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.pic_establish_irq = am18xx_intc_establish_irq,
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.pic_set_priority = am18xx_intc_set_priority,
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};
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static void *
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am18xx_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags,
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int (*func)(void *), void *arg, const char *xname)
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{
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struct am18xx_intc_softc * const sc = device_private(dev);
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const u_int irq = be32toh(specifier[0]);
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if (irq >= sc->sc_num_irqs) {
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device_printf(dev, "IRQ %u is out of range\n", irq);
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return NULL;
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}
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const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0;
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return intr_establish_xname(irq, ipl, IST_LEVEL | mpsafe, func, arg,
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xname);
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}
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static void
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am18xx_intc_fdt_disestablish(device_t dev, void *ih)
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{
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return intr_disestablish(ih);
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}
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static bool
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am18xx_intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf,
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size_t buflen)
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{
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const u_int irq = be32toh(specifier[0]);
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snprintf(buf, buflen, "irq %d", irq);
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return true;
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}
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static void
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am18xx_intc_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t mask)
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{
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struct am18xx_intc_softc * const sc = PICTOSOFTC(pic);
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const size_t group = irq_base / 32;
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uint32_t esr_reg = AM18XX_AINTC_ESR1 + 4 * group;
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INTC_WRITE(sc, esr_reg, mask);
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}
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static void
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am18xx_intc_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t mask)
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{
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struct am18xx_intc_softc * const sc = PICTOSOFTC(pic);
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const size_t group = irq_base / 32;
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uint32_t ecr_reg = AM18XX_AINTC_ECR1 + 4 * group;
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INTC_WRITE(sc, ecr_reg, mask);
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}
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static void
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am18xx_intc_establish_irq(struct pic_softc *pic, struct intrsource *is)
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{
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struct am18xx_intc_softc * const sc = PICTOSOFTC(pic);
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/* there is one CMR register per 4 interrupts*/
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uint32_t cmr_reg = AM18XX_AINTC_CMR0 + (is->is_irq & (~0x3));
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uint32_t cmr_shift = (is->is_irq % 4) * 8;
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/* update CMR register with channel */
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uint32_t cmr = INTC_READ(sc, cmr_reg);
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cmr = cmr & ~(0xFF<<cmr_shift);
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cmr |= AM18XX_AINTC_IRQ_CHANNEL << cmr_shift;
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INTC_WRITE(sc, cmr_reg, cmr);
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}
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static void
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am18xx_intc_set_priority(struct pic_softc *pic, int new_ipl)
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{
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curcpu()->ci_cpl = new_ipl;
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}
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static int
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find_pending_irqs(struct am18xx_intc_softc *sc, size_t group)
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{
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uint32_t reg = AM18XX_AINTC_SECR1 + (4 * group);
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uint32_t pending = INTC_READ(sc, reg);
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/* clear interrupts */
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INTC_WRITE(sc, reg, pending);
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if (pending == 0)
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return 0;
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return pic_mark_pending_sources(&sc->sc_pic, group * 32, pending);
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}
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static void
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am18xx_intc_irq_handler(void *frame)
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{
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struct cpu_info * const ci = curcpu();
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struct am18xx_intc_softc * const sc = intc_softc;
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const int old_ipl = ci->ci_cpl;
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const uint32_t oldipl_mask = __BIT(old_ipl);
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int ipl_mask = 0;
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ci->ci_data.cpu_nintr++;
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for (int group = 0; group <= sc->sc_num_irqs/32; group++) {
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ipl_mask |= find_pending_irqs(sc, group);
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}
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if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
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pic_do_pending_ints(I32_bit, old_ipl, frame);
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}
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/*
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* Enable interrupt according to the TRM section 11.3.2
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*/
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static void am18xx_intc_enable_interrupts(struct am18xx_intc_softc *sc)
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{
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/* disable interrupts */
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INTC_WRITE(sc, AM18XX_AINTC_GER, 0);
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INTC_WRITE(sc, AM18XX_AINTC_HIER, 0);
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/* disable nesting and prioritization in CR */
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INTC_WRITE(sc, AM18XX_AINTC_CR, 0);
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/* disable all interrupts, clear their status */
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for (int i = 0; i <= sc->sc_num_irqs / 32; i++) {
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INTC_WRITE(sc, AM18XX_AINTC_ECR1 + 4 * i, 0xFFFFFFFF);
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INTC_WRITE(sc, AM18XX_AINTC_SECR1 + 4 * i, 0xFFFFFFFF);
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}
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/* enable IRQ interrupts */
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INTC_WRITE(sc, AM18XX_AINTC_HIER, AM18XX_AINTC_HIER_IRQ);
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/* set enable bit in GER */
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INTC_WRITE(sc, AM18XX_AINTC_GER, AM18XX_AINTC_GER_ENABLE);
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}
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int
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am18xx_intc_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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void
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am18xx_intc_attach(device_t parent, device_t self, void *aux)
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{
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struct am18xx_intc_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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uint32_t maxsources;
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sc->sc_bst = faa->faa_bst;
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intc_softc = sc;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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if (of_getprop_uint32(phandle, "ti,intc-size", &maxsources) != 0) {
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aprint_error(": couldn't get max interrupt number\n");
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return;
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}
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sc->sc_num_irqs = maxsources;
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sc->sc_pic.pic_ops = &am18xx_intc_picops;
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sc->sc_pic.pic_maxsources = maxsources;
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strlcpy(sc->sc_pic.pic_name, device_xname(self),
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sizeof(sc->sc_pic.pic_name));
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pic_add(&sc->sc_pic, 0);
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fdtbus_register_interrupt_controller(self, phandle,
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&am18xx_intc_fdt_funcs);
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arm_fdt_irq_set_handler(am18xx_intc_irq_handler);
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am18xx_intc_enable_interrupts(sc);
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aprint_normal("\n");
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}
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‎sys/arch/arm/ti/files.ti‎

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@@ -12,6 +12,10 @@ device omapintc: pic, pic_splfuncs
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attach omapintc at fdt
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file arch/arm/ti/ti_omapintc.c omapintc
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device am18xxintc: pic, pic_splfuncs
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attach am18xxintc at fdt
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file arch/arm/ti/am18xx_intc.c am18xxintc
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# WakeupGen
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device omapwugen
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attach omapwugen at fdt with omapwugen

‎sys/arch/evbarm/conf/GENERIC_V5‎

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@@ -61,6 +61,7 @@ cpu* at fdt? pass 0
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# interrupt handlers
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imx23icoll* at fdt? pass 1 # imx23 interrupt driver
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am18xxintc* at fdt? pass 1 # TI AM18XX interrupt controller
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# Timers
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imx23timrot* at fdt? pass 2 # imx23 timer

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