image: assemble per-DDR-binning full NOR images for hi3516cv610/cv608 (#2208)#2210
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The cv6xx u-boot is published per DDR binning (boot-hi3516cv610-<code>-nor.bin): the boot-ROM DDR init table is baked into each boot image, and DDR training only calibrates PHY timing — it cannot detect DDR type/size. So hi3516cv610 spans three distinct topologies (DDR2-64M / DDR3-128M / DDR3-512M) with no single universal image. The create() assembly loop only handled Sigmastar/ Ingenic/Allwinner, so no full flashable NOR image was produced for cv6xx at all. Add create_hisi(): u-boot at offset 0, the pre-packed kernel+rootfs blob firmware.bin.<soc> at the firmware partition (0x50000 / 320 KiB, per the cv6xx u-boot MTDPARTS). Emit one image per DDR topology: openipc-hi3516cv610-ddr2-64m-nor-ultimate.bin openipc-hi3516cv610-ddr3-128m-nor-ultimate.bin openipc-hi3516cv610-ddr3-512m-nor-ultimate.bin openipc-hi3516cv608-nor-ultimate.bin Validated against the live latest-release artifacts: u-boot (236K) + firmware.bin (9.94M) at 0x50000 fit the 16 MiB NOR, squashfs landing at the post-image offset. Hi3519DV500 is intentionally not included yet: its NOR boot path is not wired in u-boot (CONFIG_USE_BOOTCOMMAND off, empty MTDPARTS, bootcmd "bootm <ram>"), so a full NOR image cannot boot. Refs #2208. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This was referenced Jun 27, 2026
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Closes #2208 for cv6xx (cv610/cv608).
Root cause
The cv6xx u-boot is published per DDR binning (
boot-hi3516cv610-{10b,20s,20g,00s,00g}-nor.bin,boot-hi3516cv608-nor.bin) because the boot-ROM DDR init table (reg_info.bin) is baked into each boot image.CONFIG_CMD_DDR_TRAININGis a runtime PHY-timing calibration command — it can't detect DDR type/size — so hi3516cv610 has three genuinely different topologies (DDR2-64M-QFN / DDR3-128M-QFN / DDR3-512M-BGA) and there is no single universal image.The
create()assembly loop inimage.ymlonly iterated Sigmastar/Ingenic/Allwinner and assumed oneu-boot-<soc>-nor.bin+ separateuImage/rootfs.squashfsat fixed offsets. cv6xx ships neither (its.tgzis a single pre-packedfirmware.bin.<soc>= FIT + squashfs), so no full flashable NOR image was produced for cv6xx at all — the gap behind #2208.Change
Add
create_hisi()and a cv6xx loop. Per DDR topology, assemble: u-boot at offset 0,firmware.bin.<soc>at the firmware partition (0x50000 / 320 KiB, per the cv6xx u-bootMTDPARTS "256k(boot),64k(env),…,7168k@0x50000(firmware),…"). Produces:openipc-hi3516cv610-ddr2-64m-nor-ultimate.binopenipc-hi3516cv610-ddr3-128m-nor-ultimate.binopenipc-hi3516cv610-ddr3-512m-nor-ultimate.binopenipc-hi3516cv608-nor-ultimate.bin(The
20g/00gu-boots carry the same DDR table as20s/00s, differing only in thesocmodelenv tag, so one image per DDR suffices.) Missing artifacts/manifest entries are skipped gracefully — no broken images.Validation
Assembled from the live
latest-release artifacts:boot-hi3516cv610-20s-nor.bin(236 KiB) +firmware.bin.hi3516cv6xx(9.94 MiB) at0x50000→ fits the 16 MiB NOR with the squashfs magic landing at0x310000(the post-image internal offset), u-boot reset vector at 0.Not included: Hi3519DV500
dv500's NOR boot path is not yet wired in u-boot (
# CONFIG_USE_BOOTCOMMAND is not set,CONFIG_MTDPARTS_DEFAULT="", bootcmdbootm 0x42000000with nosf read), so a full NOR image can't boot. Deferred until that lands.Follow-up candidates: QEMU full-flash-boot of an assembled cv610 image;
repack_firmware.shhisilicon support (manual flow).Refs #2208.