Software Engineer specializing in Rust, low-level systems, and distributed infrastructure.

I build systems from the ground up — from custom CPU emulators and cache simulators to Rust-based edge services processing 10M+ requests daily and event-driven fintech pipelines. Currently contributing to NVIDIA's infra-controller (NICo), an open-source bare-metal/DPU lifecycle management system.

• 🦀 High-performance systems in Rust (Tokio, Actix Web, lock-free data structures)
• ⚙️ CPU architecture — ISA design, pipeline simulation, cache modeling
• 📡 Event-driven architecture with Apache Kafka at production scale
• ☁️ Cloud-native infrastructure — Docker, Kubernetes, AWS

A large-scale Rust systems codebase for bare-metal and DPU lifecycle management. Contributing by navigating unfamiliar production code, root-causing issues with real evidence rather than assumptions, and working directly with the maintainer team.

• Diagnosed and closed a test-coverage gap in the mock BMC test harness — one hardware type had no way to be tested as a host machine at all. Added the missing test infrastructure and a regression test. (Merged)
• Found and filed a MachineId-collision bug affecting four hardware mock types, backed by reproducible test evidence; confirmed and fixed by a project maintainer.
• Traced a reported regression to its exact root cause by reproducing the failure against a real local cloud-init installation (not just reading documentation), and proposed a fix currently under maintainer review.

Stack: Rust · Tokio · PostgreSQL · Kubernetes · gRPC

Languages Rust • Python • Java • Go • C++ • TypeScript • Solidity

Backend Tokio • Actix Web • Spring Boot • FastAPI • JAX-RS • Hibernate

Infrastructure Kafka • Redis • Docker • Kubernetes • Terraform • AWS • GitHub Actions

Databases PostgreSQL • MySQL • Amazon S3 • Redshift • Snowflake

Concepts CPU architecture • Cache simulation • Pipeline hazard detection • Distributed systems • Memory safety • Concurrency • Event-driven architecture • CI/CD

A complete CPU built from first principles in Rust. Every design decision — instruction encoding, memory layout, interrupt handling — made deliberately and documented.

• Custom 35-instruction ISA with 16-bit fixed-width encoding and 5-bit FLAGS register
• Two-pass assembler with forward-reference resolution compiling .asm → binary
• 5-stage in-order pipeline (IF → ID → EX → MEM → WB) with RAW data hazard stall detection, flag hazard detection for conditional branches, and 2-cycle branch flush
• Direct-mapped write-through L1 cache classifying misses as cold vs conflict; demonstrates cache thrashing on bubble sort's non-sequential access pattern
• 6 assembly programs: bubble sort, binary search, Sieve of Eratosthenes, RPN stack calculator, Fibonacci, Factorial
• 49 integration tests · 5 versioned releases · CI: fmt + clippy + test on every push

Stack: Rust · Custom ISA · Pipeline Simulation · Cache Modeling · Systems Programming

Rust-based AI agent implementing the full plan → act → observe execution loop.

• Modular tool system with dynamic tool registration and extensibility
• Async architecture with Tokio for scalable multi-step task execution
• Memory-safe by design using Rust ownership model
• Published as a reusable library on crates.io
• ⭐ 12 stars — organic traction from the Rust community

Stack: Rust · Tokio · LLM APIs · Async

• 💼 LinkedIn: linkedin.com/in/raj-mandaliya-78a622249
• 🌐 Portfolio: rajmandaliya-portfolio.vercel.app
• ✉️ Email: rajmandaliyasurvey@gmail.com

💡 Open to System SOftware / SDE III roles in systems and backend infrastructure.