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Pull requests: Silimate/yosys

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Pull requests list

[ENG-1911] Registers should be annotated every cycle in 'sim'
#152 opened Apr 17, 2026 by stanminlee • Draft
8
Reenable VHDL
#150 opened Apr 16, 2026 by akashlevy Loading…
2
Big update from upstream
#129 opened Mar 27, 2026 by akashlevy • Draft
ProTip! Exclude everything labeled bug with -label:bug.