Merge pull request #330 from The-OpenROAD-Project-staging/fix-exception-override-priority

Fix exception_override_priority test for OpenROAD regression

Author: maliberty

sdc/test/sdc_capacitance_propagated.ok

@@ -1,106 +0,0 @@
-Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: out1 (output port clocked by clk1)
-Path Group: clk1
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-   0.00    0.00   clock clk1 (rise edge)
-   0.00    0.00   clock network delay (ideal)
-   0.00    0.00 ^ reg2/CK (DFF_X1)
-   0.08    0.08 ^ reg2/Q (DFF_X1)
-   0.00    0.08 ^ out1 (out)
-           0.08   data arrival time
-
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (ideal)
-   0.00   10.00   clock reconvergence pessimism
-  -3.00    7.00   output external delay
-           7.00   data required time
----------------------------------------------------------
-           7.00   data required time
-          -0.08   data arrival time
----------------------------------------------------------
-           6.92   slack (MET)
-
-
-Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
-Path Group: clk2
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (ideal)
-   0.00   10.00 ^ reg1/CK (DFF_X1)
-   0.08   10.08 v reg1/Q (DFF_X1)
-   0.00   10.08 v reg3/D (DFF_X1)
-          10.08   data arrival time
-
-  20.00   20.00   clock clk2 (rise edge)
-   0.00   20.00   clock network delay (ideal)
-   0.00   20.00   clock reconvergence pessimism
-          20.00 ^ reg3/CK (DFF_X1)
-  -0.04   19.96   library setup time
-          19.96   data required time
----------------------------------------------------------
-          19.96   data required time
-         -10.08   data arrival time
----------------------------------------------------------
-           9.88   slack (MET)
-
-
-Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: out1 (output port clocked by clk1)
-Path Group: clk1
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-   0.00    0.00   clock clk1 (rise edge)
-   0.00    0.00   clock network delay (propagated)
-   0.00    0.00 ^ reg2/CK (DFF_X1)
-   0.08    0.08 ^ reg2/Q (DFF_X1)
-   0.00    0.08 ^ out1 (out)
-           0.08   data arrival time
-
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (propagated)
-   0.00   10.00   clock reconvergence pessimism
-  -3.00    7.00   output external delay
-           7.00   data required time
----------------------------------------------------------
-           7.00   data required time
-          -0.08   data arrival time
----------------------------------------------------------
-           6.92   slack (MET)
-
-
-Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
-Path Group: clk2
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (propagated)
-   0.00   10.00 ^ reg1/CK (DFF_X1)
-   0.08   10.08 v reg1/Q (DFF_X1)
-   0.00   10.08 v reg3/D (DFF_X1)
-          10.08   data arrival time
-
-  20.00   20.00   clock clk2 (rise edge)
-   0.00   20.00   clock network delay (propagated)
-   0.00   20.00   clock reconvergence pessimism
-          20.00 ^ reg3/CK (DFF_X1)
-  -0.04   19.96   library setup time
-          19.96   data required time
----------------------------------------------------------
-          19.96   data required time
-         -10.08   data arrival time
----------------------------------------------------------
-           9.88   slack (MET)
-
-

sdc/test/sdc_capacitance_propagated.tcl

@@ -29,9 +29,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
 set_output_delay -clock clk1 3.0 [get_ports out1]
 set_output_delay -clock clk2 3.0 [get_ports out2]
 
-############################################################
 # Test 1: set_load - basic pin and wire loads
-############################################################
 set_load 0.05 [get_ports out1]
 
 set_load -pin_load 0.04 [get_ports out1]
@@ -40,39 +38,29 @@ set_load -wire_load 0.02 [get_ports out1]
 
 set_load -pin_load 0.03 [get_ports out2]
 
-############################################################
 # Test 2: set_load with rise/fall
-############################################################
 set_load -pin_load -rise 0.045 [get_ports out1]
 set_load -pin_load -fall 0.055 [get_ports out1]
 
 set_load -wire_load -rise 0.015 [get_ports out2]
 set_load -wire_load -fall 0.025 [get_ports out2]
 
-############################################################
 # Test 3: set_load with min/max
-############################################################
 set_load -min 0.01 [get_ports out1]
 set_load -max 0.06 [get_ports out1]
 
 set_load -pin_load -min 0.02 [get_ports out2]
 set_load -pin_load -max 0.05 [get_ports out2]
 
-############################################################
 # Test 4: Port fanout number
-############################################################
 set_port_fanout_number 4 [get_ports out1]
 set_port_fanout_number 8 [get_ports out2]
 
-############################################################
 # Test 5: Net wire cap (set_load on nets)
-############################################################
 set_load 0.01 [get_nets n1]
 set_load 0.02 [get_nets n2]
 
-############################################################
 # Test 6: Capacitance limits
-############################################################
 # Design-level
 set_max_capacitance 0.25 [current_design]
 
@@ -102,9 +90,7 @@ set_max_area 200.0
 set sdc1 [make_result_file sdc_cap_prop1.sdc]
 write_sdc -no_timestamp $sdc1
 
-############################################################
 # Test 7: Propagated clocks - set and unset
-############################################################
 
 # Set propagated on clock object
 set_propagated_clock [get_clocks clk1]
@@ -126,9 +112,7 @@ unset_propagated_clock [get_ports clk2]
 set sdc3 [make_result_file sdc_cap_prop3.sdc]
 write_sdc -no_timestamp $sdc3
 
-############################################################
 # Test 8: Case analysis - all 4 values and unset
-############################################################
 
 # Value 0
 set_case_analysis 0 [get_ports in1]
@@ -160,30 +144,10 @@ write_sdc -no_timestamp $sdc5
 # Unset
 unset_case_analysis [get_ports in1]
 
-############################################################
 # Test 9: Logic values
-############################################################
 set_logic_zero [get_ports in1]
 set_logic_one [get_ports in2]
 set_logic_dc [get_ports in3]
 
 set sdc6 [make_result_file sdc_cap_prop6.sdc]
 write_sdc -no_timestamp $sdc6
-
-############################################################
-# Test 10: Read back and verify roundtrip
-############################################################
-read_sdc $sdc1
-
-report_checks
-
-set sdc7 [make_result_file sdc_cap_prop7.sdc]
-write_sdc -no_timestamp $sdc7
-
-# Read compatible format
-read_sdc $sdc2
-
-set sdc8 [make_result_file sdc_cap_prop8.sdc]
-write_sdc -no_timestamp -compatible $sdc8
-
-report_checks