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Rename src/Instruction_Decode/RegisterFile.v to RegisterFile.sv and update references across the project. Updated Quartus QSF to treat RegisterFile.sv as a SYSTEMVERILOG_FILE (also fixed pkg_control_fsm extension to .svh), adjusted src/Instruction_Decode/Makefile SRCS and test target to use the .sv file, and modified testInstructDecode.tcl to svlog the SystemVerilog file. No functional changes to the module implemented—just tooling/build updates for SystemVerilog support.
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closes #213
This pull request refactors the codebase to introduce a new typedef,
reg_t, for register address fields (5 bits wide), and updates all relevant modules and testbenches to use this new type instead of raw[4:0]logic vectors. This improves code readability, type safety, and consistency across the project.Type definition and usage standardization:
reg_taslogic [4:0]insrc/types.svh, and included this type definition where needed. [1] [2] [3] [4]Module and interface updates:
rd,rs1,rs2,Addr1,Addr2,Addr3) to usereg_tinstead of[4:0]. This includes changes inInstruction_Decode.sv,RegisterFile.v,Logger.sv,decoder.sv,utoss_riscv.sv, and the testbenchrf_tb.sv. [1] [2] [3] [4] [5] [6]