NoC Router: RTL to GDSII Implementation

Final 1x3 Router GDSII Layout - Sky130 PDK (OpenLane Flow)

1. Introduction

NoC Router-RTL2GDSII is a fully implemented 1×3 packet router taken from Register-Transfer Level (RTL) all the way to GDSII, using the SkyWater SKY130A PDK and the OpenLane/OpenROAD digital ASIC flow.

The goal of this project is to demonstrate the complete ASIC design pipeline, including RTL architecture, functional verification, logic synthesis, physical design, and signoff.

For users new to routers and packet switching, the following video provides the foundational concept:

Khan Academy: "How the Internet Works: Routers and Packet Switching"

2. High-Level Router Architecture

This design implements a 1-input, 3-output packet router. Each packet contains:

• Header - includes a 2-bit destination address
• Payload - variable-length data
• Parity byte - used for error detection

The router includes:

Controller (FSM)

Manages the entire dataflow:

• Detects header
• Starts payload transfer
• Handles FIFO-full conditions
• Generates control signals for register & sync blocks
• Ensures correct parity sequencing

Register Block

Handles:

• Header capture
• Payload forwarding
• Internal parity calculation
• External parity storage
• Error flag generation

Synchronizer

• Latches destination address
• Decodes FIFO write enables
• Provides valid-out signals
• Manages inactivity-based soft reset per FIFO

FIFO Subsystem

Three independent FIFOs (one per output port), each implemented using:

• A developed and verified synchronous FIFO IP
• A wrapper module (wrap_fifo) that adapts the FIFO interface to the router control logic and implements router-specific control signals

Controller FSM Diagram

3. RTL Implementation

All RTL sources are under:

rtl/
├── modules/
│   ├── controller.v
│   ├── reg.v
│   ├── sync.v
│   ├── fifo.v
│   └── wrap_fifo.v
└── topmodule/
    └── router.v

Key features:

• Clean hierarchy
• FIFO reused from verified IP
• Thin wrapper to adapt to router interface
• Parameterizable FIFO depth and width

4. Functional Verification

Testbenches are located under:

tb/
├── modules/
└── topmodule/
    └── router_tb.v

The verification flow checks:

• Header decoding
• FIFO selection
• FIFO full/empty transitions
• Payload and parity sequencing
• Soft reset timeout behavior
• End-to-end packet traversal through all three output ports

Simulations generate VCD waveforms viewable in any VCD Viewer:

router_tb.vcd

5. Logic Synthesis (Yosys)

Scripts:

synth/
├── synth_router.ys
└── show_router.ys

6. Physical Design: OpenLane/OpenROAD

The project uses the Sky130A PDK and the full OpenLane flow:

• Floorplanning
• Power grid generation
• Placement
• Clock Tree Synthesis
• Global & detailed routing
• RC extraction
• Timing & physical signoff
• GDSII export

Final Layout

gds_final/router.gds   

Physical Design Artifacts

floorplan/
routing/
signoff/
gds_final/

These include DEF, SPEF, STA reports, LVS/DRC logs, and final GDS.

7. Key Results (from metrics.csv & reports)

Target Clock

• 20 ns period (50 MHz)

Timing (STA)

• No setup or hold violations
• Clean clock tree
• Stable skew and insertion delay
• All checks met

Power (Typical Corner)

From STA power report:

• Internal: 2.01e-03 mW
• Switching: 9.42e-04 mW
• Leakage: 1.71e-08 mW
• Total power ≈ 0.439 mW

Utilization

• Core Utilization: 36.29%
• Cell Count: 2,109 standard cells
• Die Area: ~0.078 mm²

Routing

• Wirelength: 71,279 units
• Vias: 17,407
• No routing violations

Signoff

• DRC: 0 violations
• LVS: Clean
• STA: Passed
• Final GDSII exported successfully

8. Directory Structure

NoCRouter-RTL2GDSII/
├── docs/
├── floorplan/
│   ├── router.def
├── gds_final/
│   ├── gds-1.png
│   ├── gds-2.png
│   ├── gds-3.png
│   └── router.gds
├── routing/
├── rtl/
│   ├── modules/
│   │   ├── controller.v
│   │   ├── fifo.v
│   │   ├── reg.v
│   │   ├── sync.v
│   │   └── wrap_fifo.v
│   └── topmodule/
│       └── router.v
├── signoff/
├── synth/
│   ├── show_router.ys
│   └── synth_router.ys
├── tb/
│   ├── modules/
│   └── topmodule/
│       └── router_tb.v
├── sta/
├── run_sim.sh
└── config.tcl

9. Running Functional Simulation & Synthesis

chmod +x run_sim.sh
./run_sim.sh

Produces:

router_tb.vcd
router_synth.v — synthesized netlist
router.svg — block-level schematic extracted by Yosys

11. OpenLane Flow (Optional)

Commands are referenced in comments inside run_sim.sh.
Requires Docker-based OpenLane pre-installed.

12. License

Open for educational and personal use under the MIT License

Reference Repositories

• 1X3 Router Design Verification
• ROUTER-1X3-RTL-DESIGN

Research Papers & Articles

• Packet Router Overview
  Covers packet routing fundamentals in computer science.
• Packet Definition
  Explains packet structure and networking basics.
• Router 1X3-RTL Design and Verification
  Initial implementation of router design and verificaiton
• Design and functional verification of 1*3 router using verilog
  Recent article on implementation and verification of 1X3 router using verilog