freertos_use_task_fpu_support set by default to 0x2 for support float#380
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freertos_use_task_fpu_support set by default to 0x2 for support float#380Partokus wants to merge 1 commit into
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Question on adaptivesupport.amd.com: https://adaptivesupport.amd.com/s/feed/0D5Pd00001VvcoWKAR?language=en_US I programming cortex r5 processor on Xilinx Zynq us+ and i faced problem with garbage and impossible values in float and double. I spend WHOLE WEEK finding cause of this problem. Issue was in FreeRTOS config setting "freertos_use_task_fpu_support" (configUSE_TASK_FPU_SUPPORT). By default it set to value "1". It meens that tasks DON'T support FPU context saving when switch context between tasks. I set it to "2" and problem solved. I using 5 freertos tasks and it was crucial for me. My question is: Why in Xilinx BSP drivers in lib freertos there "freertos_use_task_fpu_support" is set to "1" by default? Okey, it increase speed of context switch between tasks, but who cares? I don't think default people want to get max speed of switch context. It is rare case when developer want to speed up context switch. Xilinx Zynq US+ very powerfull and speedy processor... Can we think about set this option by default to "2" in Xilinx BSP drivers?
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Question on adaptivesupport.amd.com:
https://adaptivesupport.amd.com/s/feed/0D5Pd00001VvcoWKAR?language=en_US
I programming cortex r5 processor on Xilinx Zynq us+ and i faced problem with garbage and impossible values in float and double.
I spend WHOLE WEEK finding cause of this problem. Issue was in FreeRTOS config setting "freertos_use_task_fpu_support" (configUSE_TASK_FPU_SUPPORT). By default it set to value "1". It meens that tasks DON'T support FPU context saving when switch context between tasks. I set it to "2" and problem solved. I using 5 freertos tasks and it was crucial for me.
My question is:
Why in Xilinx BSP drivers in lib freertos there "freertos_use_task_fpu_support" is set to "1" by default? Okey, it increase speed of context switch between tasks, but who cares? I don't think default people want to get max speed of switch context. It is rare case when developer want to speed up context switch. Xilinx Zynq US+ very powerfull and speedy processor... Can we think about set this option by default to "2" in Xilinx BSP drivers?