systems & hardware · IIIT Bangalore
Most interesting thing i did till now: https://blog.janestreet.com/asic-puzzle-results/ - Ctrl + F and find my name "Lokesh Aravapalli"
C++ FPGA HLS ASIC SystemVerilog Computer Architecture
systems & hardware · IIIT Bangalore
Most interesting thing i did till now: https://blog.janestreet.com/asic-puzzle-results/ - Ctrl + F and find my name "Lokesh Aravapalli"
C++ FPGA HLS ASIC SystemVerilog Computer Architecture
got featured in JANESTREET Blog for this submission
This project implements the Radix-2 Fast Fourier Transform (FFT) algorithm on an FPGA using Xilinx DSP48 IP blocks. The design leverages the parallel processing capabilities of FPGAs to achieve hig…
Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.
This is the ELCIA (2024) hackathon entry by Team SLL to develop a refreshable braille display.
Python 1
Forked from anirudh-pathaneni/HealthCare-with-Alerts-Summarizer
Python