Update layout-checklist.md

layout-checklist.md

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 ## General
 
 * [ ] [Schematic review](schematic-checklist.md) complete and signed off, including pin swaps done during layout
-* [ ] Layout DRC 100% clean
+* [ ] Layout DRC 100% clean, verified against the finalized netlist and board layer stackup parameters.
 
 ## Decoupling
 
-* [ ] Decoupling caps as close to power pins as possible
-* [ ] Low inductance mounting used for decoupling (prefer ViP if available, otherwise "[]8" shaped side vias)
+* [ ] Decoupling caps as close to power pins as possible, prioritizing the smallest value, highest frequency capacitor closest to the component pad.
+* [ ] Low inductance mounting used for decoupling ensuring vias are positioned symmetrically to minimize the loop area.
 
 ## DFM / yield enhancement
 
-* [ ] All design rules within manufacturer's capability
-* [ ] Minimize use of vias/traces that push fab limits
-* [ ] Controlled impedance specified in fab notes if applicable
-* [ ] Confirm impedance calculations include soldermask, or mask removed from RF traces
-* [ ] Stackup verified with manufacturer and specified in fab notes
-* [ ] Board finish specified in fab notes
-* [ ] If panelizing, add panel location indicators for identifying location-specific reflow issues
-* [ ] (recommended) Layer number markers specified to ensure correct assembly
-* [ ] Fiducials present (on both sides of board) if targeting automated assembly
-* [ ] Fiducial pattern asymmetric to detect rotated or flipped boards
-* [ ] Soldermask/copper clearance on fiducials respected
-* [ ] Panelization specified if required
+* [ ] All design rules within manufacturer's capability (trace width, spacing, minimum drill, and annular ring requirements).
+* [ ] Minimize use of vias/traces that push fab limits to avoid manufacturing yield degradation.
+* [ ] Controlled impedance specified in fab notes if applicable, referencing the specific layer and nominal target metrics 50 ohms, 90 ohms, 100 ohms.
+* [ ] Confirm impedance calculations include soldermask effects, or mask removed from high-frequency microwave or RF traces.
+* [ ] Stackup verified with manufacturer and specified in fab notes, explicitly defining layer thicknesses and core/prepreg material types.
+* [ ] Board finish specified in fab notes (ENIG, HASL, OSP) matching the pitch requirements of the component selection.
+* [ ] If panelizing, add panel location indicators for identifying location-specific reflow or wave soldering thermal profiles.
+* [ ] (recommended) Layer number markers specified on the copper layers to ensure correct stackup assembly order at the fab house.
+* [ ] Fiducials present (on both sides of board) if targeting automated assembly, clear of all traces and fills.
+* [ ] Fiducial pattern asymmetric across the board to detect rotated or flipped boards in the pick-and-place machine.
+* [ ] Soldermask/copper clearance on fiducials respected, creating an unmasked clearance zone of at least 3x the fiducial diameter.
+* [ ] Panelization specified if required, including breakout tabs, mouse bites, and tooling pin positions.
 
 ## Footprints
 
-* [ ] Confirm components are available in the selected package
-* [ ] Confirm components (especially connectors and power regulators) are capable of desired current in the selected package
-* [ ] Verify schematic symbol matches the selected package
-* [ ] Confirm pinout diagram is from top vs bottom of package
-* [ ] FPC connectors: Verify top/bottom entry and validate pinout
-* [ ] (recommended) PCB printed 1:1 on paper and checked against physical parts
-* [ ] 3D models obtained (if available) and checked against footprints
-* [ ] Soldermask apertures on all SMT lands and PTH pads
+* [ ] Confirm components are available in the selected package and active in the supply chain lifecycle.
+* [ ] Confirm components (especially connectors and power regulators) are capable of desired current in the selected package, verifying thermal pad contact requirements.
+* [ ] Verify schematic symbol matches the selected package pinout, ordering suffixes, and landing dimensions exactly.
+* [ ] Confirm pinout diagram is from top vs bottom of package to prevent mirrored assembly errors.
+* [ ] FPC connectors: Verify top/bottom entry and validate pinout direction against the mating cable assembly.
+* [ ] (recommended) PCB printed 1:1 on paper and checked against physical parts to confirm component spacing and body profiles.
+* [ ] 3D models obtained (if available) and checked against footprints to flag mechanical height violations and connector keep-outs.
+* [ ] Soldermask apertures on all SMT lands and PTH pads are fully defined and scaled to fabrication tolerances.
 
 ## Differential pairs
-* [ ] Routed differentially
-* [ ] Skew matched
-* [ ] Correct clearance to non-coupled nets
+
+* [ ] Routed differentially with symmetric trace tracking, avoiding uncoupled stubs or sharp 90 degree directional changes.
+* [ ] Skew matched within interface timing budgets, adding matching patterns close to the point where the skew is introduced.
+* [ ] Correct clearance to non-coupled nets maintained at a minimum of 3x the trace width 3W rule to reduce crosstalk.
+* [ ] Route differential lines symmetrically over an unbroken reference ground plane, avoiding any underlying plane voids.
 
 ## High-speed signals
 
-* [ ] Sufficient clearance to potential aggressors
-* [ ] Length matched if required
-* [ ] Minimize crossing reference plane splits/slots or changing layers, use caps/stitching vias if unavoidable
-* [ ] Confirm fab can do copper to edge of PCB for edge launch connectors
-* [ ] Double-check pad width on connectors and add plane cutouts if needed to minimize impedance discontinuities
-* [ ] Add stitching vias to ground plane in large top layer ground pads (SMA etc) to avoid resonances
+* [ ] Sufficient clearance to potential aggressors (clocks, switching rails) enforced via physical guard separations.
+* [ ] Length matched if required by bus architecture constraints, keeping compensation patterns compact.
+* [ ] Enforce 45-degree bends instead of 90-degree corners to minimize acute angle acid traps during fabrication and reduce high-frequency impedance discontinuities.
+* [ ] Minimize crossing reference plane splits/slots or changing layers; use high-frequency stitching caps or adjacent ground stitching vias if layer changes are unavoidable to preserve the return path.
+* [ ] Double-check pad width on connectors and add reference plane cutouts directly underneath the pads if needed to minimize capacitive impedance discontinuities.
+* [ ] Add stitching vias to ground plane in large top layer ground pads (SMA etc) to avoid high-frequency skin-effect resonances and path impedance mismatches.
+* [ ] High-speed single-ended lines and clocks should be embedded on internal layers sandwiched between continuous ground planes (stripline routing) to contain EMI radiations.
 
 ## Power
-* [ ] Minimal slots in planes from via antipads
-* [ ] Sufficient width for planes/traces for required current
 
+* [ ] Minimal slots in planes from via antipads, ensuring overlapping antipads do not construct unintentional slots that choke plane return currents.
+* [ ] Sufficient width for planes/traces for required current, calculated using IPC-2152 standards for temperature rise limits.
+* [ ] Shape plane transitions, neck-downs, and thick trace corners using 45-degree cuts or soft corners to maintain uniform current density and prevent thermal hotspots.
+* [ ] Place input filtration capacitors immediately adjacent to the high dI/dt input loop of switching regulators to constrain magnetic fields.
+* [ ] Ensure switching nodes (SW) on regulators are kept as physically short and wide as possible to minimize electric field radiation surfaces.
+
 ## Sensitive analog
-* [ ] Guard ring / EMI cages provided if needed
-* [ ] Physically separated from high current SMPS or other noise sources
-* [ ] Consider microphone effect on MLCCs if near strong sound sources
+
+* [ ] Guard ring / EMI cages provided if needed, isolated cleanly from digital switching currents.
+* [ ] Physically separated from high current SMPS or other noise sources, ensuring analog traces never run parallel to digital clock paths.
+* [ ] Consider microphone effect on MLCCs if near strong sound or high-vibration sources; substitute with tantalum or film options in audio/sensor paths.
+* [ ] Run high-resolution analog inputs as differential or shielded routing configurations to prevent noise pickup from nearby logic banks.
+
+## EMI / EMC (Layout Extensions)
+
+* [ ] Provide a continuous, unbroken reference ground plane directly beneath all active high-speed, digital, and clock distribution layers.
+* [ ] Enforce the (20H) rule on power planes, pulling the edges of power distribution copper layers back from the ground plane boundary to suppress edge radiation emissions.
+* [ ] Isolate the chassis ground copper from the circuit digital ground plane by an explicit, continuous keep-out slot, bridging them only through designated filter networks.
+* [ ] Route external I/O signals through local interface filters before allowing the traces to route deep into the core circuit logic.
+* [ ] Place common-mode chokes and ESD suppression arrays immediately at the entrance of the physical connector pins, avoiding any filter-bypassing routing paths.
+* [ ] Avoid routing any signal line across an isolated split reference plane boundary without high-frequency stitching structures.
+* [ ] Terminate unused copper pours with stitching vias tied back to the primary ground plane to prevent ungrounded copper floating islands from acting as resonant antennas.
 
 ## Mechanical
-* [ ] Confirm all connectors to other systems comply with the appropriate mechanical standard (connector orientation, key position, etc)
-* [ ] LEDs, buttons, and other UI elements on outward-facing side of board
-* [ ] Keep-outs around PCB perimeter, card guides, panelization mouse-bites, etc respected
-* [ ] Stress-sensitive components (MLCC) sufficiently clear from V-score or mouse bite locations, and oriented to reduce
-bending stress
-* [ ] Clearance around large ICs for heatsinks/fans if required
-* [ ] Clearance around pluggable connectors for mating cable/connector
-* [ ] Clearance around mounting holes for screws
-* [ ] Plane keepouts and clearance provided for shielded connectors, magnetics, etc
-* [ ] Confirm PCB dimensions and mounting hole size/placement against enclosure or card rack design
-* [ ] Verify mounting hole connection/isolation
-* [ ] Components not physically overlapping/colliding
-* [ ] Clearance provided around solder-in test points for probe tips
-* [ ] Mounting hole positions compatible with enclosure design rules (keepouts around bends/welds etc respected)
+
+* [ ] Confirm all connectors to other systems comply with the appropriate mechanical standard (connector orientation, key position, mating direction, etc).
+* [ ] LEDs, buttons, and other UI elements on outward-facing side of board or matching enclosure windows.
+* [ ] Keep-outs around PCB perimeter, card guides, panelization mouse-bites, and mounting margins fully respected.
+* [ ] Stress-sensitive components (MLCC) sufficiently clear from V-score or mouse bite locations, and oriented parallel to stress lines to reduce bending fracture risks.
+* [ ] Clearance around large ICs for heatsinks/fans if required, checking for vertical clearance constraints.
+* [ ] Clearance around pluggable connectors for mating cable/connector shroud tolerances.
+* [ ] Clearance around mounting holes for screws and hand tools, ensuring washers do not crush nearby traces.
+* [ ] Plane keepouts and clearance provided for shielded connectors, magnetics, and transformers to prevent secondary noise coupling.
+* [ ] Confirm PCB dimensions and mounting hole size/placement against enclosure or card rack design using imported STEP data.
+* [ ] Verify mounting hole connection/isolation, matching schematic logic grounding choices exactly.
+* [ ] Components not physically overlapping/colliding with each other or adjacent mechanical structures.
+* [ ] Clearance provided around solder-in test points for tester probe tips and alignment guides.
+* [ ] Mounting hole positions compatible with enclosure design rules (keepouts around bends/welds etc respected).
 
 ## Thermal
 
-* [ ] Thermal reliefs used for plane connections (unless via is used for heatsinking)
-* [ ] Solid connections used to planes if heatsinking
-* [ ] Ensure thermal balance on SMT chip components to minimize risk of tombstoning
+* [ ] Thermal reliefs used for plane connections (unless via is used for heatsinking) to ensure uniform solder heat profiles.
+* [ ] Solid connections used to planes if heatsinking, dropping stitching via clusters through inner copper plane expansions to maximize lateral dissipation.
+* [ ] Ensure thermal balance on SMT chip components to minimize risk of tombstoning during reflow cycles.
 
 ## Solder paste
 
-* [ ] No uncapped vias in pads (except low-power QFNs where some voiding is acceptable)
-* [ ] QFN paste prints segmented
-* [ ] Small pads 100% size, larger pads reduced to avoid excessive solder volume
-* [ ] No paste apertures on card edge connectors or test points
+* [ ] No uncapped vias in pads (except low-power QFNs where some voiding is acceptable) to prevent solder wicking down via barrels.
+* [ ] QFN paste prints segmented into a multi-window pattern to prevent component lifting caused by volatile outgassing.
+* [ ] Small pads 100% size, larger pads reduced to avoid excessive solder volume and component shifting.
+* [ ] No paste apertures on card edge connectors or test points.
 
 ## Solder mask
 
-* [ ] Confirm SMD vs NSMD pad geometry
-* [ ] Adequate clearance around pads (typ. 50 um)
+* [ ] Confirm SMD vs NSMD pad geometry against package specifications to meet target registration tolerances.
+* [ ] Adequate clearance around pads (typ. 50 um) to maintain soldermask dam structural integrity and avoid solder bridging.
 
 ## Silkscreen
 
-* [ ] Text size within fab limits
-* [ ] Text not overlapping drills or component pads
-* [ ] Text removed entirely in, or moved outside of, high component/via density areas
-* [ ] Traceability markings (rev, date, name, etc) provided
-* [ ] Silkscreen box provided for writing/sticking serial number
-* [ ] Text mirrored properly on bottom layer
-* [ ] Test points labeled if space permits
+* [ ] Text size within fab limits for line width and character height.
+* [ ] Text not overlapping drills, test points, or component landing pads.
+* [ ] Text removed entirely in, or moved outside of, high component/via density areas to guarantee legible markings.
+* [ ] Traceability markings (rev, date, name, compliance logos) provided in highly visible zones.
+* [ ] Silkscreen box provided for writing/sticking serial numbers or barcode tags.
+* [ ] Text mirrored properly on the bottom layer to ensure correct reading direction post-assembly.
+* [ ] Test points and diagnostic vectors clearly labeled if board space permits.
 
 ## Flex specific
-* [ ] Components oriented to reduce bending forces
-* [ ] Teardrops on all wire-to-pad connections
+
+* [ ] Components oriented to reduce bending forces, avoiding placement directly along active structural bend lines.
+* [ ] Teardrops on all wire-to-pad connections to avoid stress concentration cracks at conductor trace transitions.
 
 ## CAM production
-* [ ] KiCAD specific: rerun DRC and zone fills before exporting CAM files to ensure proper results
-* [ ] Export gerber/drill files at the same time to ensure consistency
-* [ ] Visually verify final CAM files to ensure no obvious misalignments
+
+* [ ] KiCAD / Altium specific: rerun DRC and zone fills immediately before exporting CAM files to ensure copper geometry changes update properly.
+* [ ] Export gerber/drill files at the same time to ensure alignment consistency across production layers.
+* [ ] Visually verify final CAM files in a standalone Gerber viewer to ensure no obvious misalignments, missing mask clearances, or layout inversions exist.