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| Idx | Sensor | Project Status | Interface | Project Link | FPGA | IDE | FPS (MAX) | Resolution |
Target |
|---|---|---|---|---|---|---|---|---|---|
| 1 | IMX415 | 🟢 DONE | MIPI | IMX415 | Cyclone V SoC | Quartus Prime | 60 | 3840 |
60 |
| 2 | IMX291 | 🟢 DONE | MIPI | IMX291 | Cyclone V SoC | Quartus Prime | 60 | 1920 |
60 |
| 3 | OV4689 | 🟢 DONE | MIPI | OV4689 | Cyclone V SoC | Quartus Prime | 60 | 1344 |
60 |
| 4 | OV13850 | 🟢 DONE | MIPI | OV13850 | Cyclone V SoC | Quartus Prime | 30 | 3840 |
30 |
For Vivado, using block diagram method is very userfriendly!
However, please pay GOOD attention to the reset polarity!
| Idx | Sensor | Project Status | Interface | Project Link | FPGA | IDE | FPS (MAX) | Resolution |
Target |
|---|---|---|---|---|---|---|---|---|---|
| 1 | OV13850 | 🟢 DONE | MIPI | OV13850 | Xilinx |
Vivado |
30 | 4224 |
30 |
| 2 | OV4689 | 🟢 DONE | MIPI | OV4689 | Xilinx |
Vivado |
90 | 2688 |
30 |
| 3 | IMX291 | 🟢 DONE | MIPI | IMX291 | Xilinx |
Vivado |
120 | 1920 |
60 |
| 4 | OV5640 | 🟢 DONE | DVP | OV5640 | Xilinx |
Vivado |
30 | 1920 |
30 |
| 5 | OV5640 | 🟢 DONE | DVP | OV5640 | Xilinx |
Vivado |
30 | 1920 |
30 |
| 6 | OV5640 | 🟢 DONE | DVP | OV5640 | Xilinx |
Vivado |
30 | 1920 |
60 |
| 7 | OV5640 | 🟢 DONE | DVP | OV5640 | Xilinx |
Vivado |
30 | 1920 |
30 |
| 8 | OV5640 | 🟢 Done | DVP | OV5640 | Xilinx |
Vivado |
30 | 1920 |
30 |
| 9 | OV5640 | 🟢 Done | DVP | OV5640 | Xilinx |
Vivado |
30 | 1920 |
30 |
| 10 | OV2640 | 🟢 DONE | DVP | OV2640 | Xilinx |
Vivado |
30 | 800 |
30 |
| 11 | OV7670 | 🟢 DONE | DVP | OV7670 | Xilinx |
Vivado |
30 | 640 |
30 |
| 12 | OV9655 | 🟢 DONE | DVP | OV9655 | Xilinx |
Vivado |
30 | 640 |
30 |
| 13 | OV7740 | 🟢 DONE | DVP | OV7740 | Xilinx |
Vivado |
60 | 640 |
60 |