Ph.D. candidate at The Hong Kong University of Science and Technology (Guang Zhou)
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The Hong Kong University of Science and Technology (GuangZhou)
- https://chestercc1997.github.io
Highlights
- Pro
Pinned Loading
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Gy-Hu/E-Syn
Gy-Hu/E-Syn PublicE-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
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Gy-Hu/E-Syn2
Gy-Hu/E-Syn2 PublicE-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)
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yosys_rtl-netlist_sequential_cec
yosys_rtl-netlist_sequential_cec PublicYosys & ABC script for sequential equivalence checking for RTL and Synthesized netlist
Verilog 7
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