Fix: reject implicit data types in data_declaration

[0ncorhynchus]

This PR fixes #118.

Summary

This change ensures that implicit data types in data_declaration are rejected unless the var keyword is explicitly used.
This aligns the parser behavior with the SystemVerilog standard and prevents ambiguous parsing inside procedural blocks.

Changes

• Add verify logic to reject implicit data types in data_declaration_variable when var is not used.
• Add unit tests validating the updated behavior.
• Update several spec tests to reflect correct SystemVerilog parsing rules.

Notes on Spec Tests

Some spec tests were previously validating the parsing of procedural assignments as module_items.
However, such statements are illegal at the module scope according to the SystemVerilog LRM.

This incorrect behavior was caused by treating identifier-leading procedural assignments as implicit declarations.

This PR corrects that behavior, and the affected spec tests have been updated accordingly.

[dalance]

Thank you for your contribution!
I'll merge this PR.