arm64: dts: phytium: Add dts for Phytium SoCs#1730
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Add initial device tree nodes for Phytium pd2308 SoC with support of on-chip devices. Signed-off-by: Zhou Yulin <zhouyulin1283@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>
Add initial device tree for Phytium Pd2408 SoCs. Signed-off-by: Chen Zhenhua <chenzhenhua@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>
Add initial device tree nodes for Phytium Ps2316 SoC with support of 16 cores, gicv3 interrupt controller, serial port, PCIe host etc. Signed-off-by: Wang Xu <wangxu@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>
Add SCMI power domain descriptions to the GPU, DCDP, VPU, SCE, and NPU nodes to support SCMI power domain management. Signed-off-by: Peng Min <pengmin1540@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>
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Hi @mamingrui123. Thanks for your PR. I'm waiting for a deepin-community member to verify that this patch is reasonable to test. If it is, they should reply with Once the patch is verified, the new status will be reflected by the I understand the commands that are listed here. DetailsInstructions for interacting with me using PR comments are available here. If you have questions or suggestions related to my behavior, please file an issue against the kubernetes/test-infra repository. |
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Does Documention needs update too? |
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/approve |
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[APPROVALNOTIFIER] This PR is APPROVED This pull-request has been approved by: Avenger-285714 The full list of commands accepted by this bot can be found here. The pull request process is described here DetailsNeeds approval from an approver in each of these files:
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Pull request overview
This PR adds Device Tree Source (DTS) files for several new Phytium ARM64 SoCs (pd2408, pd2308, ps2316) and their corresponding development boards. It registers the new dtb targets in the existing phytium Makefile.
Changes:
- Add new SoC dtsi files:
pd2408-generic-psci-soc.dtsi,pd2308.dtsi,ps2316-generic-psci-soc.dtsi. - Add board dts files:
pd2408-devboard-d4-dsk.dts,pd2308-demo-a.dts,pd2308-demo-b.dts,ps2316-devboard-16c-dsk.dts. - Update
arch/arm64/boot/dts/phytium/Makefileto build the new dtb targets whenCONFIG_ARCH_PHYTIUMis enabled.
Reviewed changes
Copilot reviewed 8 out of 8 changed files in this pull request and generated 33 comments.
Show a summary per file
| File | Description |
|---|---|
| arch/arm64/boot/dts/phytium/pd2408-generic-psci-soc.dtsi | New SoC DT for Phytium pd2408 with CPUs, GIC, SCMI, audio, USB, PCIe, etc. |
| arch/arm64/boot/dts/phytium/pd2408-devboard-d4-dsk.dts | Board DT enabling pd2408 SoC peripherals. |
| arch/arm64/boot/dts/phytium/pd2308.dtsi | New SoC DT for Phytium pd2308. |
| arch/arm64/boot/dts/phytium/pd2308-demo-a.dts | Demo board A overlay for pd2308. |
| arch/arm64/boot/dts/phytium/pd2308-demo-b.dts | Demo board B overlay for pd2308. |
| arch/arm64/boot/dts/phytium/ps2316-generic-psci-soc.dtsi | New SoC DT for Phytium ps2316. |
| arch/arm64/boot/dts/phytium/ps2316-devboard-16c-dsk.dts | Board DT for ps2316 16-core development board. |
| arch/arm64/boot/dts/phytium/Makefile | Add the new dtb targets. |
Comments suppressed due to low confidence (2)
arch/arm64/boot/dts/phytium/pd2408-devboard-d4-dsk.dts:199
- The standard
statusvalues are"okay"and"disabled". While"ok"was supported as a deprecated alias, current DT specifications anddtcwarn about it. The codebase mixes"ok"(in board override blocks) with"okay"(e.g.mmc0). Prefer"okay"consistently across all these new board dts files (pd2408-devboard-d4-dsk.dts,ps2316-devboard-16c-dsk.dts,pd2308-demo-a.dts,pd2308-demo-b.dts).
&uart0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&uart2 {
status = "ok";
};
&mmc0 {
bus-width = <0x00000008>;
max-frequency = <1000000>;
cap-mmc-hw-reset;
cap-mmc-highspeed;
no-sdio;
no-sd;
non-removable;
status = "okay";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&i2c2 {
status = "ok";
};
&i2c3 {
status = "ok";
};
&sata {
status = "ok";
};
&usb3_0 {
status = "ok";
};
&usb3_1 {
status = "ok";
};
&usb3_2 {
status = "ok";
};
&usb3_3 {
status = "ok";
};
&usb3_4 {
status = "ok";
};
&usb2_0 {
status = "ok";
};
&usb2_1 {
status = "ok";
};
&pcie {
status = "ok";
};
&qspi0 {
status = "ok";
};
&spi0 {
status = "ok";
};
&spi1 {
status = "ok";
};
&gpio0 {
status = "ok";
};
&gpio1 {
status = "ok";
};
&pwm0 {
phytium,db = <0 0 0 1000 1000 0>;
status = "ok";
};
&i2s0 {
status = "ok";
};
&gmac0 {
status = "ok";
};
&npu {
status = "ok";
};
&virt_gmac0 {
status = "ok";
};
&virt_i2s0 {
status = "ok";
};
&virt_gmac0 {
status = "ok";
};
&virt_uart0 {
status = "ok";
};
&virt_uart1 {
status = "ok";
};
&virt_uart2 {
status = "ok";
};
&virt_mmc0 {
bus-width = <0x00000008>;
max-frequency = <1000000>;
cap-mmc-hw-reset;
cap-mmc-highspeed;
no-sdio;
no-sd;
non-removable;
status = "ok";
};
&virt_i2c0 {
status = "ok";
};
&virt_i2c1 {
status = "ok";
};
&virt_i2c2 {
status = "ok";
};
&virt_i2c3 {
status = "ok";
};
&virt_spi0 {
status = "ok";
};
&virt_spi1 {
status = "ok";
};
arch/arm64/boot/dts/phytium/pd2308-demo-a.dts:15
- The
compatiblestring"phytium,pd2308"is the same as the SoC compatible. Board dts files conventionally include a more-specific board compatible first followed by the SoC compatible, e.g.compatible = "phytium,pd2308-demo-a", "phytium,pd2308";(as done inpd2408-devboard-d4-dsk.dts).
compatible = "phytium,pd2308";
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| i2s_dp0@0x26cc2000 { | ||
| compatible = "phytium,i2s"; | ||
| reg = <0x0 0x26cc2000 0x0 0x1000 0x0 0x26cc3000 0x0 0x1000>; | ||
| interrupts = <0 70 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp2"; | ||
| }; |
| <0x0 0x26feB000 0x0 0x1000>; | ||
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | ||
| clocks = <&sysclk_100mhz>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| virt_i2c1: i2c@2701a000 { //smbus1 | ||
| compatible = "phytium,i2c_iop"; | ||
| reg = <0x0 0x2701a000 0x0 0x1000>, | ||
| <0x0 0x26fec000 0x0 0x1000>; | ||
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | ||
| clocks = <&sysclk_100mhz>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| status = "disabled"; | ||
| }; | ||
|
|
||
| virt_i2c2: i2c@2701b000 { //pmbus0 | ||
| compatible = "phytium,i2c_iop"; | ||
| reg = <0x0 0x2701b000 0x0 0x1000>, | ||
| <0x0 0x26feD000 0x0 0x1000>; |
| clocks = <&sysclk_100mhz>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
|
| dcFTD330@0x26ca0000 { | ||
| compatible = "phytium,dc-1.0"; | ||
| reg = <0x0 0x26ca0000 0x0 0x1e000 0x00 0x26fcc080 0x00 0x20>; | ||
| interrupts = <0x0 0x37 0x4 0x0 0x3a 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4>; | ||
| pipe_mask = [03]; | ||
| edp_mask = [00]; | ||
| overlay_enable = <0x00>; | ||
| memory-region = <0x19>; | ||
| water_mark = <0x5666 0x5666 0x5666>; | ||
| qos = <0xf0 0xf0 0xf0>; | ||
| phy_mode = <0x01 0x01 0x01>; | ||
| power-domains = <&scmi_power 0x1f &scmi_power 0x20>; | ||
| #address-cells = <0x1>; | ||
| #size-cells = <0x0>; | ||
| }; | ||
|
|
||
| vpu { | ||
| compatible = "phytium,vpu"; | ||
| reg = <0x0 0x26c88000 0x0 0x10000 0x0 0x26fcc0a0 0x0 0x40>; | ||
| interrupts = <0x0 0x1c 0x4>, <0x0 0x1d 0x4>; | ||
| memory-region = <0x20>; | ||
| power-domains = <&scmi_power 0x25 &scmi_power 0x26>; | ||
| }; | ||
|
|
||
|
|
||
| i2s_dp0@26cbe000 { | ||
| compatible = "phytium,i2s"; | ||
| reg = <0x0 0x26cbe000 0x0 0x1000 0x0 0x26cbf000 0x0 0x1000>; | ||
| interrupts = <0 68 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp0"; | ||
| }; | ||
|
|
||
| i2s_dp1@0x26cc0000 { | ||
| compatible = "phytium,i2s"; | ||
| reg = <0x0 0x26cc0000 0x0 0x1000 0x0 0x26cc1000 0x0 0x1000>; | ||
| interrupts = <0 69 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp1"; | ||
| }; | ||
|
|
||
| i2s_dp0@0x26cc2000 { | ||
| compatible = "phytium,i2s"; | ||
| reg = <0x0 0x26cc2000 0x0 0x1000 0x0 0x26cc3000 0x0 0x1000>; | ||
| interrupts = <0 70 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp2"; | ||
| }; | ||
|
|
||
| virt_i2s_dp0@0x2701f000 { | ||
| compatible = "phytium,virt-i2s"; | ||
| reg = <0x0 0x2701f000 0x0 0x1000>, | ||
| <0x0 0x26fe0000 0x0 0x1000>, | ||
| <0x0 0x26cbf000 0x0 0x1000>; | ||
| interrupts = <0 68 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp0"; | ||
| }; | ||
|
|
||
| virt_i2s_dp1@0x27020000 { | ||
| compatible = "phytium,virt-i2s"; | ||
| reg = <0x0 0x27020000 0x0 0x1000>, | ||
| <0x0 0x26fe1000 0x0 0x1000>, | ||
| <0x0 0x26cc1000 0x0 0x1000>; | ||
| interrupts = <0 69 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp1"; | ||
| }; | ||
|
|
||
| virt_i2s_dp2@0x27021000 { | ||
| compatible = "phytium,virt-i2s"; | ||
| reg = <0x0 0x27021000 0x0 0x1000>, | ||
| <0x0 0x26fe2000 0x0 0x1000>, | ||
| <0x0 0x26cc3000 0x0 0x1000>; | ||
| interrupts = <0 70 4>; | ||
| clocks = <&sysclk_600mhz>; | ||
| clock-names = "i2s_clk"; | ||
| dai-name = "phytium-i2s-dp2"; | ||
| }; |
| buffer@0 { | ||
| no-map; | ||
| reg = <0x21 0x10000000 0x0 0x8000000>; | ||
| phandle = <0x19>; | ||
| }; | ||
|
|
||
| buffer@10 { | ||
| no-map; | ||
| reg = <0x21 0x20000000 0x0 0x40000000>; | ||
| phandle = <0x18>; | ||
| }; | ||
|
|
||
| buffer@20 { | ||
| no-map; | ||
| reg = <0x21 0x60000000 0x0 0x40000000>; | ||
| phandle = <0x20>; |
| 0x0 0x0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | ||
| ranges = <0x1000000 0x00 0x00 0x0 0x50000000 0x0 0xf00000>, | ||
| <0x2000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, | ||
| <0x3000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; |
|
|
||
| pmdk_dp { | ||
| compatible = "phytium,pmdk-dp"; | ||
| num-dp = <0x00000003>; |
| device_type = "cpu"; | ||
| compatible = "arm,armv8"; | ||
| reg = <0x0 0x200>; | ||
| enable-method = "psci"; | ||
| numa-node-id = <0>; | ||
| clocks = <&scmi_dvfs 2>; | ||
| }; | ||
|
|
||
| cpu_b0: cpu@300 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,armv8"; | ||
| reg = <0x0 0x300>; | ||
| enable-method = "psci"; | ||
| numa-node-id = <0>; | ||
| clocks = <&scmi_dvfs 3>; | ||
| }; | ||
|
|
||
| cpu_l3: cpu@10000 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,armv8"; | ||
| reg = <0x0 0x10000>; | ||
| enable-method = "psci"; | ||
| numa-node-id = <0>; | ||
| clocks = <&scmi_dvfs 4>; | ||
| }; | ||
|
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||
| cpu_l4: cpu@10100 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,armv8"; | ||
| reg = <0x0 0x10100>; | ||
| enable-method = "psci"; | ||
| numa-node-id = <0>; | ||
| clocks = <&scmi_dvfs 5>; | ||
| }; | ||
|
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||
| cpu_l5: cpu@10200 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,armv8"; | ||
| reg = <0x0 0x10200>; | ||
| enable-method = "psci"; | ||
| numa-node-id = <0>; | ||
| clocks = <&scmi_dvfs 6>; | ||
| }; | ||
|
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| cpu_b1: cpu@10300 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,armv8"; | ||
| reg = <0x0 0x10300>; | ||
| enable-method = "psci"; | ||
| numa-node-id = <0>; | ||
| clocks = <&scmi_dvfs 7>; | ||
| }; |
| method = "smc"; | ||
| cpu_suspend = <0xc4000001>; | ||
| cpu_off = <0x84000002>; | ||
| cpu_on = <0xc4000003>; | ||
| sys_poweroff = <0x84000008>; | ||
| sys_reset = <0x84000009>; |
| */ | ||
|
|
||
| /dts-v1/; | ||
| /memreserve/ 0x80000000 0x10000; |
Add dts for Phytium SoCs.