[codex] warn when layout is missing Board macro

[lucia3e8]

Summary

• Warn when pcb layout builds a schematic that has no root Board/layout_path, instead of silently doing nothing.
• Render the warning with Ariadne at the insertion point and include a concrete Board(...) suggestion derived from the .zen filename.
• Add an integration snapshot test for the warning output.

Why

Without a root board declaration, layout generation has no destination directory, so pcb layout returns successfully without producing files. The new warning explains that requirement and gives the user a directly usable board declaration.

Validation

• cargo fmt
• cargo test -p pcb --test layout
• cargo run -p pcb -- layout --no-open boost_5v.zen from examples/os_13_4

---

Note

Low Risk
Low risk: adds a non-fatal CLI warning path when layout generation produces no output, plus tests; minimal impact on core layout sync behavior.

Overview
pcb layout now emits an Ariadne-rendered warning when layout generation returns no result and the schematic lacks a root Board macro with a string layout_path, including a suggested Board(...) insertion derived from the .zen filename.

Adds ariadne as a dependency, updates the changelog entry, and introduces snapshot tests covering missing/invalid layout_path cases.

^{Reviewed by Cursor Bugbot for commit c69899f. Bugbot is set up for automated code reviews on this repo. Configure here.}

[github-actions]

Build Performance

Board	Base (median)	Head (median)	Change
demo/DM0001	239ms ±8	242ms ±10	+1.3%
demo/DM0002	185ms ±3	195ms ±5	+5.1%
demo/DM0003	244ms ±3	258ms ±4	1.05× ±0.02 slower
demo/Feign	170ms ±18	172ms ±3	+1.2%
demo/Renfield	166ms ±1	167ms ±2	+0.8%
demo/Seward	168ms ±3	167ms ±2	-0.7%
arduino/Nano	161ms ±2	161ms ±2	+0.1%
arduino/UNOQ	367ms ±10	363ms ±19	-1.0%

_{Measured with hyperfine. Times show median ±stddev.}

[devin-ai-integration]

✅ Devin Review: No Issues Found

Devin Review analyzed this PR and found no potential bugs to report.

View in Devin Review to see 2 additional findings.

[akhilles]

--- STDERR ---
Warning: layout generation needs a root `Board` macro with `layout_path`
   ╭─[ bad_layout_path.zen:6:24 ]
   │
 6 │ signal = Net("SIGNAL")
   │                        │ 
   │                        ╰─ insert the board declaration here
   │ 
   │ Help: add this to bad_layout_path.zen:
   │           Board(name="bad_layout_path", layers=4, layout_path="layout/bad_layout_path")
───╯

span should probably point to a new line