Skip to content
View ed766's full-sized avatar

Achievements

Achievement: Pull Shark

Achievements

Achievement: Pull Shark

Block or report ed766

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
ed766/README.md

SoC Design Verification Portfolio

I build report-backed RTL and verification projects with SystemVerilog, UVM, Verilator, C/C++/SystemC reference models, assertions, formal checks, Python automation, and open-source implementation tools. The portfolio is deliberately separated by verification scope rather than repeating the same claims across projects.

Project Primary specialty Selected measured evidence Review
RISC-V Chiplet SoC Firmware-driven subsystem integration, DMA, UPF, low power, CDC 70 / 70 stable; 12 / 12 firmware; 26 / 26 power; 4 / 4 CDC Metrics · CI · v1.1.1
AXI4 L1 Cache DV Cache microarchitecture, C++ replay, replacement/error checking, SECDED RAS 22 / 22 directed; 127 / 127 replay; 55 / 55 crosses; 7 / 7 RAS Metrics · CI · v0.3.2
AXI4 QoS Fabric DV Reusable UVM/VIP, AXI concurrency, SystemC replay, QoS/fairness 8 / 8 UVM; 130 / 130 replay; 24 / 24 advanced crosses; 72 / 72 QoS points Metrics · CI · v0.3.1

Skills Matrix

Area Chiplet SoC L1 cache QoS fabric
System integration RV32 firmware, APB MMIO, DMA, AES service CPU/cache/AXI memory path Four-initiator/four-target shared fabric
Verification methodology Procedural closure plus supporting UVM/RAL C++ trace replay and mutation-driven debug Principal real-UVM lane and reusable AXI agents
Architecture depth UPF, retention/isolation, async CDC Replacement, maintenance, associativity, SECDED IDs, out-of-order responses, QoS, aging, fairness
Independent models Python/C transaction and CRC models Cycle-independent C++ cache model SystemC/TLM arbitration and routing model
Evidence Firmware, power, formal, CDC, coverage Stress, crosses, RAS, performance, synthesis proxy UVM, VIP self-test, QoS dashboard, CDC, formal 
flowchart LR
  SOC["RISC-V chiplet\nfirmware + low power"] --> PORT["Subsystem DV portfolio"]
  L1["AXI4 L1 cache\nmicroarchitecture + RAS"] --> PORT
  FAB["AXI4 QoS fabric\nUVM/VIP + concurrency"] --> PORT
Loading

All headline metrics are generated from checked-in canonical reports. These projects demonstrate open-source engineering evidence, not UCIe/AXI certification or commercial UPF, CDC, timing, and formal signoff.

Popular repositories Loading

  1. ucie_chiplet_soc ucie_chiplet_soc Public

    Firmware-driven dual-die RV32 chiplet SoC with GCC/ISS co-verification, DMA/AES offload, UPF 4.0 low-power intent, async CDC, real UVM, formal, and open-source coverage.

    SystemVerilog 9 1

  2. RISC-V RISC-V Public archive

    Superseded lightweight RISC-V model; current SoC verification work is maintained in ed766/ucie_chiplet_soc.

    SystemVerilog

  3. ed766 ed766 Public

    Open-source SoC design-verification portfolio covering firmware-driven chiplet integration, cache microarchitecture/RAS, and reusable AXI4 UVM/VIP.

    Python

  4. Flexible-Adder-Designs Flexible-Adder-Designs Public

    SystemVerilog

  5. RISC-V-SoC-with-Multi-Domain-Power-Intent-using-LibreLane RISC-V-SoC-with-Multi-Domain-Power-Intent-using-LibreLane Public archive

    Superseded historical RISC-V/low-power iteration; current work is maintained in ed766/ucie_chiplet_soc.

    SystemVerilog

  6. AXI4-L1-Cache-DV AXI4-L1-Cache-DV Public

    A 4 KiB write-back L1 cache with independent C++ trace replay, SECDED RAS, replacement/error verification, assertions, mutations, coverage, and associativity tradeoffs.

    Python