|
| 1 | +use bit_field::BitField; |
| 2 | +use core::marker::PhantomData; |
| 3 | + |
| 4 | +use crate::{RvmHal, RvmResult}; |
| 5 | + |
| 6 | +const APIC_FREQ_MHZ: u64 = 1000; // 1000 MHz |
| 7 | +const APIC_CYCLE_NANOS: u64 = 1000 / APIC_FREQ_MHZ; |
| 8 | + |
| 9 | +/// Local APIC timer modes. |
| 10 | +#[derive(Debug, Copy, Clone)] |
| 11 | +#[repr(u8)] |
| 12 | +#[allow(dead_code)] |
| 13 | +pub enum TimerMode { |
| 14 | + /// Timer only fires once. |
| 15 | + OneShot = 0b00, |
| 16 | + /// Timer fires periodically. |
| 17 | + Periodic = 0b01, |
| 18 | + /// Timer fires at an absolute time. |
| 19 | + TscDeadline = 0b10, |
| 20 | +} |
| 21 | + |
| 22 | +/// A virtual local APIC timer. (SDM Vol. 3C, Section 10.5.4) |
| 23 | +pub struct ApicTimer<H: RvmHal> { |
| 24 | + lvt_timer_bits: u32, |
| 25 | + divide_shift: u8, |
| 26 | + initial_count: u32, |
| 27 | + last_start_ns: u64, |
| 28 | + deadline_ns: u64, |
| 29 | + _phantom: PhantomData<H>, |
| 30 | +} |
| 31 | + |
| 32 | +impl<H: RvmHal> ApicTimer<H> { |
| 33 | + pub(crate) const fn new() -> Self { |
| 34 | + Self { |
| 35 | + lvt_timer_bits: 0x1_0000, // masked |
| 36 | + divide_shift: 0, |
| 37 | + initial_count: 0, |
| 38 | + last_start_ns: 0, |
| 39 | + deadline_ns: 0, |
| 40 | + _phantom: PhantomData, |
| 41 | + } |
| 42 | + } |
| 43 | + |
| 44 | + /// Check if an interrupt generated. if yes, update it's states. |
| 45 | + pub fn check_interrupt(&mut self) -> bool { |
| 46 | + if self.deadline_ns == 0 { |
| 47 | + false |
| 48 | + } else if H::current_time_nanos() >= self.deadline_ns { |
| 49 | + if self.is_periodic() { |
| 50 | + self.deadline_ns += self.interval_ns(); |
| 51 | + } else { |
| 52 | + self.deadline_ns = 0; |
| 53 | + } |
| 54 | + !self.is_masked() |
| 55 | + } else { |
| 56 | + false |
| 57 | + } |
| 58 | + } |
| 59 | + |
| 60 | + /// Whether the timer interrupt is masked. |
| 61 | + pub const fn is_masked(&self) -> bool { |
| 62 | + self.lvt_timer_bits & (1 << 16) != 0 |
| 63 | + } |
| 64 | + |
| 65 | + /// Whether the timer mode is periodic. |
| 66 | + pub const fn is_periodic(&self) -> bool { |
| 67 | + let timer_mode = (self.lvt_timer_bits >> 17) & 0b11; |
| 68 | + timer_mode == TimerMode::Periodic as _ |
| 69 | + } |
| 70 | + |
| 71 | + /// The timer interrupt vector number. |
| 72 | + pub const fn vector(&self) -> u8 { |
| 73 | + (self.lvt_timer_bits & 0xff) as u8 |
| 74 | + } |
| 75 | + |
| 76 | + /// LVT Timer Register. (SDM Vol. 3A, Section 10.5.1, Figure 10-8) |
| 77 | + pub const fn lvt_timer(&self) -> u32 { |
| 78 | + self.lvt_timer_bits |
| 79 | + } |
| 80 | + |
| 81 | + /// Divide Configuration Register. (SDM Vol. 3A, Section 10.5.4, Figure 10-10) |
| 82 | + pub const fn divide(&self) -> u32 { |
| 83 | + let dcr = self.divide_shift.wrapping_sub(1) as u32 & 0b111; |
| 84 | + (dcr & 0b11) | ((dcr & 0b100) << 1) |
| 85 | + } |
| 86 | + |
| 87 | + /// Initial Count Register. |
| 88 | + pub const fn initial_count(&self) -> u32 { |
| 89 | + self.initial_count |
| 90 | + } |
| 91 | + |
| 92 | + /// Current Count Register. |
| 93 | + pub fn current_counter(&self) -> u32 { |
| 94 | + let elapsed_ns = H::current_time_nanos() - self.last_start_ns; |
| 95 | + let elapsed_cycles = (elapsed_ns / APIC_CYCLE_NANOS) >> self.divide_shift; |
| 96 | + if self.is_periodic() { |
| 97 | + self.initial_count - (elapsed_cycles % self.initial_count as u64) as u32 |
| 98 | + } else if elapsed_cycles < self.initial_count as u64 { |
| 99 | + self.initial_count - elapsed_cycles as u32 |
| 100 | + } else { |
| 101 | + 0 |
| 102 | + } |
| 103 | + } |
| 104 | + |
| 105 | + /// Set LVT Timer Register. |
| 106 | + pub fn set_lvt_timer(&mut self, bits: u32) -> RvmResult { |
| 107 | + let timer_mode = bits.get_bits(17..19); |
| 108 | + if timer_mode == TimerMode::TscDeadline as _ { |
| 109 | + return rvm_err!(Unsupported); // TSC deadline mode was not supported |
| 110 | + } else if timer_mode == 0b11 { |
| 111 | + return rvm_err!(InvalidParam); // reserved |
| 112 | + } |
| 113 | + self.lvt_timer_bits = bits; |
| 114 | + self.start_timer(); |
| 115 | + Ok(()) |
| 116 | + } |
| 117 | + |
| 118 | + /// Set Initial Count Register. |
| 119 | + pub fn set_initial_count(&mut self, initial: u32) -> RvmResult { |
| 120 | + self.initial_count = initial; |
| 121 | + self.start_timer(); |
| 122 | + Ok(()) |
| 123 | + } |
| 124 | + |
| 125 | + /// Set Divide Configuration Register. |
| 126 | + pub fn set_divide(&mut self, dcr: u32) -> RvmResult { |
| 127 | + let shift = (dcr & 0b11) | ((dcr & 0b1000) >> 1); |
| 128 | + self.divide_shift = (shift + 1) as u8 & 0b111; |
| 129 | + self.start_timer(); |
| 130 | + Ok(()) |
| 131 | + } |
| 132 | + |
| 133 | + const fn interval_ns(&self) -> u64 { |
| 134 | + (self.initial_count as u64 * APIC_CYCLE_NANOS) << self.divide_shift |
| 135 | + } |
| 136 | + |
| 137 | + fn start_timer(&mut self) { |
| 138 | + if self.initial_count != 0 { |
| 139 | + self.last_start_ns = H::current_time_nanos(); |
| 140 | + self.deadline_ns = self.last_start_ns + self.interval_ns(); |
| 141 | + } else { |
| 142 | + self.deadline_ns = 0; |
| 143 | + } |
| 144 | + } |
| 145 | +} |
0 commit comments